能帮忙解释下么

laoniu710642

能帮忙解释下么 [复制链接]

file:///C:/Documents%20and%20Settings/Administrator/桌面/未命名.jpg][img=http:///C:/Documents%20and%20Settings/Administrator/桌面/未命名.jpg[/img]LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TEST IS
PORT(CLK,CLR:IN BIT;
D:IN bit;
Q,QN:OUT bit
);

END test;


ARCHITECTURE T OF TEST ISfile:///C:/Documents%20and%20Settings/Administrator/桌面/未命名.jpg
SIGNAL QI:BIT;
BEGIN
QN<=d after 2 us;


PROCESS(CLR,CLK)
BEGIN
IF CLR='1' THEN QI<='0' AFTER 2 US;
ELSIF (CLK'EVENT AND CLK='1') THEN
Q<=D AFTER 4 US;
END IF;
END PROCESS;
END t;

不知道为什么Q的仿真是这样 至少在第一个转变为高电平处 我就不太理解 因为D根本就没有持续高电平4 US 按书上语法而言就要忽略

图中CLK的周期是2 US

C:/Documents%20and%20Settings/Administrator/桌面/未命名1.jpg

531496955

图？