安路SparkRoad实现vga显示屏

冒险武者

安路SparkRoad实现vga显示屏 [复制链接]

 

VGA(Video Graphics Adapter)接口也是D-Sub接口的俗称，是一种采用模拟信号传输的接口；VGA指的是显示器640X480等显示模式，VGA技术的应用还主要基于VGA显示卡的计算机、笔记本等设备；上面共有 15 针孔，分成三排，每排五个。比较重要的是RGB 彩色分量信号和 扫描同步信号 HSYNC 和 VSYNC 针。

扫描时序如下所示：

  

现在就用FPGA实现VGA功能

// Define colors RGB--8|8|8
`define RED		24'hFF0000 
`define GREEN	24'h00FF00 
`define BLUE  	24'h0000FF 
`define WHITE 	24'hFFFFFF 
`define BLACK 	24'h000000 
`define YELLOW	24'hFFFF00 
`define CYAN  	24'hFF00FF 
`define ROYAL 	24'h00FFFF 

// Define Display Mode

module vga_dis
#(
	parameter H_DISP = 800,
	parameter V_DISP = 600
)
( 
	input  wire	 		clk,
	input  wire	 		clk_108m,	
	input  wire			rst_n,	
	
	//user interface
	output wire	[11:0]	lcd_xpos,		//lcd horizontal coordinate
	output wire	[11:0]	lcd_ypos,		//lcd vertical coordinate
//	output wire         lcd_en ,
	input  wire	[23:0]	usr_data,		//lcd datard_n  ,
	
	//localbus
    input  wire         cpu_cs_n  ,
    input  wire         cpu_wr_n  ,
    input  wire         cpu_rd_n  ,
    input  wire  [7:0]  cpu_addr  ,
    input  wire  [15:0] cpu_datain,
    output reg   [15:0] cpu_dataout,
    
    //lcd interface
	output wire			lcd_dclk,   	//lcd pixel clock
	output wire			lcd_hs,	    	//lcd horizontal sync
	output wire			lcd_vs,	    	//lcd vertical sync
	output wire			lcd_en,			//lcd display enable
	output wire	[23:0]	lcd_rgb		//lcd display data
	
);

reg  [2:0]  vga_mode;
reg  [23:0] usr_lcd_data ;
reg  [23:0]	lcd_data	;//lcd data

wire	[11:0]	lcd_xpos;	//lcd horizontal coordinate
wire	[11:0]	lcd_ypos;	//lcd vertical coordinate
	  
//read                                                     
always@(posedge clk or posedge rst_n)                        
begin                                                      
    if(rst_n == 1'b0)                                        
    begin                                                  
      cpu_dataout  <=  16'h0000;                           
    end                                                    
    else if((cpu_cs_n == 1'b0)&&(cpu_rd_n == 1'b0))        
    begin                                                  
      case(cpu_addr[7:0])                                  
         8'h00:  cpu_dataout  <=  vga_mode ; 
         8'h01:  cpu_dataout  <=  usr_lcd_data[15:0] ; 
         8'h02:  cpu_dataout  <=  usr_lcd_data[23:16] ;                           
      default:  cpu_dataout  <=  16'h0000;                 
      endcase                                              
    end                                                    
    else                                                   
      cpu_dataout  <=  16'h0000;                           
end                                                        
                                                           
//read                                                     
always@(posedge clk or posedge rst_n)                        
begin                                                      
    if(rst_n == 1'b0)                                        
    begin                                                  
      vga_mode  <=  3'b100; 
      usr_lcd_data   <= 24'h0;                                                              
    end                                                    
    else if((cpu_cs_n == 1'b0)&&(cpu_wr_n == 1'b0))        
    begin                                                  
      case(cpu_addr[7:0])                                  
         8'h00:  vga_mode  <= cpu_datain[2:0] ;    
         8'h01:  usr_lcd_data[15:0]  <= cpu_datain ; 
         8'h02:  usr_lcd_data[23:16]  <= cpu_datain[7:0] ;                           
      default: ;                                           
      endcase                                              
    end                                                    
    else ;                                                 
end                                                        

always@(posedge clk_108m or negedge rst_n)
begin
	if(!rst_n)
		lcd_data <= 24'h0;
	else 
	begin
		case(vga_mode)
		    3'b000:begin
		        if	(lcd_ypos >= 0 && lcd_ypos < (V_DISP/8)*1)
		        	lcd_data <= `RED;
		        else if(lcd_ypos >= (V_DISP/8)*1 && lcd_ypos < (V_DISP/8)*2)
		        	lcd_data <= `GREEN;
		        else if(lcd_ypos >= (V_DISP/8)*2 && lcd_ypos < (V_DISP/8)*3)
		        	lcd_data <= `BLUE;
		        else if(lcd_ypos >= (V_DISP/8)*3 && lcd_ypos < (V_DISP/8)*4)
		        	lcd_data <= `WHITE;
		        else if(lcd_ypos >= (V_DISP/8)*4 && lcd_ypos < (V_DISP/8)*5)
		        	lcd_data <= `BLACK;
		        else if(lcd_ypos >= (V_DISP/8)*5 && lcd_ypos < (V_DISP/8)*6)
		        	lcd_data <= `YELLOW;
		        else if(lcd_ypos >= (V_DISP/8)*6 && lcd_ypos < (V_DISP/8)*7)
		        	lcd_data <= `CYAN;
		        else
			lcd_data <= `ROYAL;
		    end
		    3'b001:begin
		        if	(lcd_xpos >= 0 && lcd_xpos < (H_DISP/8)*1)
		        	lcd_data <= `RED;
		        else if(lcd_xpos >= (H_DISP/8)*1 && lcd_xpos < (H_DISP/8)*2)
		        	lcd_data <= `GREEN;
		        else if(lcd_xpos >= (H_DISP/8)*2 && lcd_xpos < (H_DISP/8)*3)
		        	lcd_data <= `BLUE;
		        else if(lcd_xpos >= (H_DISP/8)*3 && lcd_xpos < (H_DISP/8)*4)
		        	lcd_data <= `WHITE;
		        else if(lcd_xpos >= (H_DISP/8)*4 && lcd_xpos < (H_DISP/8)*5)
		        	lcd_data <= `BLACK;
		        else if(lcd_xpos >= (H_DISP/8)*5 && lcd_xpos < (H_DISP/8)*6)
		        	lcd_data <= `YELLOW;
		        else if(lcd_xpos >= (H_DISP/8)*6 && lcd_xpos < (H_DISP/8)*7)
		        	lcd_data <= `CYAN;
		        else
		        	lcd_data <= `ROYAL;
		    end
		    3'b010:begin
		        lcd_data <= lcd_xpos * lcd_ypos;
		    end
		    3'b011:begin
		        if(lcd_ypos < V_DISP/2)                                       
                	lcd_data <= {lcd_ypos[7:0], lcd_ypos[7:0], lcd_ypos[7:0]};
                else                                                          
                	lcd_data <= {lcd_xpos[7:0], lcd_xpos[7:0], lcd_xpos[7:0]};
		    end
		    3'b100:begin                                 
                	lcd_data <= usr_data;
		    end
		    3'b101:begin                                 
                	lcd_data <= usr_lcd_data;
		    end
		    default lcd_data <= lcd_data;
		endcase		    
	end
end
 
                            
vga_dri  u_vga_dri                               
(                                              
// Input                                       
	.clk			(clk_108m 				),	
	.rst_n			(rst_n					), 
	.lcd_data		(lcd_data				), 
// Output 	                                   
	.lcd_dclk		(lcd_dclk				),	
	.lcd_hs			(lcd_hs	 				),	
	.lcd_vs			(lcd_vs	 				), 
	.lcd_en			(lcd_en	 				),	
	.lcd_rgb		(lcd_rgb                ),	
	.lcd_xpos		(lcd_xpos				),	
	.lcd_ypos		(lcd_ypos				)  
);                                             
 

endmodule

 

同样是采用localbus接口，可以设置不同的显示模式，目前实现5种模式实现VGA的显示样式，同时也可以通过串口，显示不同的颜色。

 

e39bd70d403aa4875a8d66bfc9b56d42

 

lugl4313820

能把显示驱动起来，接下来的东西就更好玩了吧。