【求助】用Quartus II做一个计数状态机仿真

1244334644

【求助】用Quartus II做一个计数状态机仿真 [复制链接]

 

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity FSM is
port (clk,reset,en : in std_logic;
    state_current : out integer range 0 to 3);
end FSM;
architecture behv of FSM is
type FSM_ST is (IDLE,s1,s2);
signal c_st,next_state: FSM_ST :=IDLE; --设定初态

begin
    tran: process (reset,clk) begin
      if reset='0' then c_st<=IDLE;
       elsif clk='1' and clk'event then c_st<=next_state;end if;
    end process tran;
    
    change: process(c_st,en) 
    variable a2,a3 : std_logic_vector(2 downto 0);

    begin
        case c_st is
          when IDLE => if en='1' then next_state <= s1;else next_state<=IDLE;end if;
          
          when s1 => if en='1' then a2 := a2 + 1; else next_state<=s1;end if;
                         if a2=5 then a2 := (others=>'0'); next_state <= s2;end if;
                        
          when s2 => if en='1' then a3 := a3 + 1;else next_state<=s2;end if;
                         if a3=7 then a3 := (others=>'0');next_state <= IDLE;end if;        
                         
          when others => next_state <=IDLE;
        end case;
    end process change;
    
    outstate: process(c_st) begin
        case c_st is
            when IDLE => state_current <= 1;
            when s1 => state_current <= 2;
            when s2 => state_current <= 3;
            when others => state_current <= 0;
        end case;
    end process outstate;
end behv;

这仿真出来的与要求不一致的😂，实在是找不到错在哪了。

zhangdaoyu

Quartus II的程序十来年没有写过了，现在主要应用在哪方面哪个行业呢

1244334644

zhangdaoyu 发表于 2022-4-2 11:13 Quartus II的程序十来年没有写过了，现在主要应用在哪方面哪个行业呢

主要是EDA这个行业

1244334644

知道了，没有给a2与a3赋初值