; Make sure that TLB & cache are consistent
mov r0, #0
mcr p15, 0, r0, c8, c7, 0 ; flush both TLB
mcr p15, 0, r0, c7, c5, 0 ; invalidate instruction cache
mcr p15, 0, r0, c7, c6, 0 ; invalidate data cache
mcr大概了解一下,是从r0中传值到c8 ,但是不是很明白究竟是什么意思?
有人能详细解释一下吗?
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