ep9302的一个疑问，困扰了我很久，没有办法解决！

bjanzhuang

ep9302的一个疑问，困扰了我很久，没有办法解决！ [复制链接]

ep9302的3个外部中断是如何设置的，有没有相关资料。在用户手册中没有说明。现在我遇到来一个脉冲竟然中断两次！！希望哪位大侠能帮我解决一下，小弟不胜感激！

axlylee

这要看中断方式的，电平触发？边沿触发？是上升沿 还是下降沿？

nov30th

就是不知道如何设置，没有相关资料啊。

hurton

The interrupt controller allows up to 54 interrupts to
generate an Interrupt Request (IRQ) or Fast Interrupt
Request (FIQ) signal to the processor core. Thirty-two
hardware priority assignments are provided for assisting
IRQ vectoring, and two levels are provided for FIQ
vectoring. This allows time critical interrupts to be
processed in the shortest time possible. Internal
interrupts may be programmed as active high or active
low level sensitive inputs. GPIO pins programmed as
interrupts may be programmed as active high level
sensitive, active low level sensitive, rising edge triggered,
falling edge triggered, or combined rising/falling edge
triggered.

xuejinwenxia

中断可能会被编程为高电平或低电平触发。 用GPIO来编程控制 是高电平 低电平 上升沿触发下降沿触发，或合并上升/下降沿

wangchen_0626

谢谢您的回复！
我所说的是三个外部中断32、33、34。不是EGPIO中断
Three dedicated off-chip interrupt lines operate as
active high level sensitive interrupts
看了一整篇就只有这么一句话描述。

xiawenjin

高电平有效,电平触发.

在你的ISR里面,向产生中断的外部设备给出一个信号,表示已经开始对它服务,那个外部设备需要在收到这个信号后立即撤销中断状态.

wfx198410

对于某些相对简单的设备,使用一个能在上升沿产生中断的GPIO要方便些.

born

An interrupt vector may be overwritten when two interrupts occur simultaneously. If a
VIC2 interrupt is immediately followed by a VIC1 interrupt, the VIC1 address will
incorrectly be the default handler address for 2 HCLK cycles. To work around this
problem, first check for pending non-vectored VIC1 interrupts in the interrupt routine. If
there are none then return from interrupt. The interrupt will immediately re-occur with the
correct vector address.

肖勇

上面这段话是什么意思，怎么看到不明白。我改成GPIO上升沿触发中断，也存在这个问题。所以看到这段描述觉的是不是这个问题。

tom_peng

应该不是这个问题.

这段话在说它的VIC硬件的BUG...感觉他说的有些矛盾.

一般来说这样的BUG是很难遇到的.