液晶时序的问题

yaxuangela

液晶时序的问题 [复制链接]

一个1602显示最简单的3个字符 1 2 3 ，不知道是不是时序不对， 有经验的人能帮我看看不，我外部晶振是24m，搞不明白为什么会不显示

还有就是我用了global的声明，但好像LIBRARY altera;
USE altera.altera_primitives_components.all这句话的颜色很奇怪啊，是不是这个global器件没起作用啊，但仿真好像又没啥问题。

程序如下：

--LCD状态机控制条件简单程序
--只显示已存入常量的几个数
--port : clk,rs,rw,e,q

LIBRARY IEEE;
LIBRARY altera;
USE altera.altera_primitives_components.all;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY LCD1602 IS
PORT ( CLK      : IN STD_LOGIC;    --24M
       RESET:   IN STD_LOGIC;
       lcd_RS   : OUT STD_LOGIC;
       LCD_RW   : OUT STD_LOGIC;
       LCD_E    : OUT STD_LOGIC;
       Q        : OUT STD_LOGIC_VECTOR(0 TO 7);
       LED      : OUT STD_LOGIC );
END LCD1602;

ARCHITECTURE ONE OF LCD1602 IS

TYPE LCDSTATE IS( SEETYPE,OPENDOWN,INPUTTYPE,CLEAR,SETDDRAM,WRITEDATA0,WRITEDATA1,WRITEDATA2);  --各个状态：
--设置显示方式，显示开关设置，输入方式设置，清屏，设置DDRAM地址，输入数据1，输入数据2，输入数据3

TYPE RAM IS ARRAY(0 TO 2) OF STD_LOGIC_VECTOR(0 TO 7);
CONSTANT DIGIT : RAM:=("00110000","00110001","00110010");          
SIGNAL   OUTBUFFER:STD_LOGIC_VECTOR(0 TO 7);
SIGNAL   CURRENT_STATE,NEXT_STATE：LCDSTATE;
SIGNAL   count:STD_LOGIC_vector(14 downto 0);
signal   CLK_INT: std_logic;
signal lcd_state:std_logic;
signal lcd_en:std_logic;
signal   lcd_rss:std_logic;
signal clk_int0:std_logic;
component global

    port (

        a_in : in std_logic;

        a_out : out std_logic);

end component;

BEGIN

process(clk,reset)    --使能时序
begin
   if(reset='0')then
     count<=(others=>'0');
   elsif(clk'event and clk='1') then
       if(count<23999) then
         count<=count+1;
        else count<=(others=>'0');
        end if;
   end if;
end process;
 process(count,reset)
 begin
 if(reset='0')
 then LCD_state<='0';
  elsif(count<12000)
   then LCD_state<='0';
   else
        LCD_state<='1';
   end if;
end process;

process( count,reset)
 begin
  if(reset='0')
   then LCD_en<='0';
    elsif(count<3000)
      then LCD_en<='1';
     elsif(count<15000)
       then LCD_en<='0';
       else
          LCD_en<='1';
  end if;
end process;

process( clk)
begin
 if(clk'event and clk='1')
  then clk_int0<=LCD_state;
 end if;
end process;
u:global port map(a_in=>clk_int0,a_out=>clk_int);

process( clk)
 begin
  if(clk'event and clk='1')
   then LCD_E<=LCD_en;
  end if;
end process;

 

 LED<=clk_int;
 lcd_rss <= '1' when CURRENT_STATE =WRITEDATA0 OR CURRENT_STATE=WRITEDATA1 OR CURRENT_STATE=WRITEDATA2 else '0';
 lcd_rw <= '0';
process(clk_int)
begin
if clk_int'event and clk_int='1' then lcd_rs<=lcd_rss;
end if;
end process;

--并行过程
REG: PROCESS(CLK_int,RESET)--时序进程
BEGIN
  IF RESET='0' THEN  CURRENT_STATE<= SEETYPE;
    ELSIF CLK_int'EVENT AND CLK_int='1' THEN CURRENT_STATE<=NEXT_STATE;
  END IF;
END PROCESS reg;

COM: PROCESS(CURRENT_STATE) --状态转换进程
 BEGIN
 CASE CURRENT_STATE IS
   WHEN  seetype    => next_STATE<=opendown;
   when  opendown   => next_STATE<=inputtype;
   when  inputTYPE  => next_STATE<=clear;
   when  clear      => next_STATE<=setddram;
   when  setddram   => next_STATE<=writedata0;
   when  writedata0 => next_STATE<=writedata1;
   when  writedata1 =>  next_STATE<=writedata2;
   when  writedata2 =>  next_STATE<=seetype;
   when others      =>   next_STATE<=seetype;
 end case;
end process com;

com1: process(current_state) --状态译码进程
   begin
 case current_state is
   when seetype    =>  OUTBUFFER<="00111000";
   when opendown   =>  OUTBUFFER<="00001111";
   when inputTYPE  =>  OUTBUFFER<="00000110";
   when clear      =>  OUTBUFFER<="00000001";
   when setddram   =>  OUTBUFFER <="10000000";
   when writedata0 =>  outbuffer<=digit(0);
   when writedata1 =>  OUTBUFFER<=digit(1);
   when writedata2 =>  outbuffer<=digit(2);
   when others     =>  OUTBUFFER<=null;

 end case;
end process com1;

latch: process( clk_int) -- 寄存器进程
 begin
  IF CLK_INT'EVENT AND CLK_INT='1'  THEN
 Q<=OUTBUFFER;
  END IF;
 END PROCESS LATCH;

END ONE;

 

[ 本帖最后由 yaxuangela 于 2010-7-23 11:00 编辑 ]

范小川

楼主很猛啊。用FPGA做1602。

yaxuangela

不是1602，只是用1602来搞明白fpga里面液晶的控制，还有其他模块的，只是还没写而已，    有谁熟悉啊，帮帮忙啊。