MSP430Fr6972--AD使用小结

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MSP430Fr6972--AD使用小结 [复制链接]

#include<msp430.h>

int main(void)
{
  WDTCTL = WDTPW | WDTHOLD;                 // Stop WDT

  // GPIO Setup
  P1OUT &= ~(BIT4 |BIT5);                           // Clear LED to start
  P1DIR |= (BIT4 | BIT5);                            // P1.4/5 output
  
  //1.采样引脚配置
  ///配置为AD功能，P1.0~3（A0~3）、P9.4~7(A12~15)均可以复用为AD采样功能
  P1SEL1 |= BIT3;                           
  P1SEL0 |= BIT3;                           /// Configure P1.3 for ADC：
                                            
  // Disable the GPIO power-on default high-impedance mode to activate
  // previously configured port settings
  PM5CTL0 &= ~LOCKLPM5;

  //2.参考电压配置
  // By default, REFMSTR=1 => REFCTL is used to configure the internal reference
  while(REFCTL0 & REFGENBUSY);              // If ref generator busy, WAIT
  REFCTL0 |= REFVSEL_1 | REFON;             // Select internal ref = 2.0V
                                            // Internal Reference ON
                                            //详见《user's guide》24.3.1

  ///3.ADC相关寄存器配置
  // Configure ADC12
  //ADC12CTL0~2控制寄存器
  ADC12CTL0 = ADC12SHT0_2 | ADC12ON;        // 采样保持时间16ADCCLK；启动AD(在ADC12ENC=0的情况下，修改启动或关闭AD)
  ADC12CTL1 = ADC12SHP;                     // ADCCLK = MODOSC; sampling timer  ： 从采样保持器中获取信号
  ADC12CTL2 |= ADC12RES_2;                  // 12-bit conversion results分辨率
  ADC12CTL3 |=ADC12CSTARTADD_5;             //选择ADC12MCTL5控制
  ADC12IER0 |= ADC12IE5;                    // Enable ADC conv complete interrupt(ADC12MEM5)

  //////////////////////////////////////////////////////////////////////////////
  //AD使用总结：
  //详见《user's guide》Figure 25-1 ADC12_B模块图
  //AD有32个独立采样通道A0~A31，即ADC12INCH_x选择哪个通道，这个通道与IO引脚对应，详见《datasheet》Table 4-1. Pin Attributes
      //P1.3引脚对应A3，所以这里使用ADC12INCH_3
  
  //ADC12MCTL0~31对应32个通道管理寄存器，管理响应的AD转换结果保存寄存器ADC12MEM0~31，使用哪个寄存器保存结果用ADC12CSTARTADD_x设置
      //例：ADC12CTL3 |=ADC12CSTARTADD_5;//选择ADC12MCTL5控制ADC12MEM5保存AD转换结果
      //ADC12IER0 |= ADC12IE5;中断与响应寄存器对应
      //注：ADC12MEM0~31与AD有32个独立采样通道A0~A31不需要一一对应使用
         //本例中A3通道使用的就是ADC12MEM5,即：ADC12MEMx可以任意分配给不同的通道，详见Figure 25-1
  //////////////////////////////////////////////////////////////////////////////
  ADC12MCTL5 |= ADC12INCH_3 | ADC12VRSEL_1;   //ADC12INCH_3  : 通道3   ////    ADC12VRSEL_1   :内部参考电压

  //4.等待参考电压配置完成
  while(!(REFCTL0 & REFGENRDY));            // Wait for reference generator to settle

  while(1)
  {
    //5.Ad采样并获得结果  注：AD采样是需要时间的，加上延时
    __delay_cycles(5000);                    // Delay between conversions
    ADC12CTL0 |= ADC12ENC | ADC12SC;         // Sampling and conversion start

    __bis_SR_register(LPM0_bits + GIE);      // LPM0, ADC10_ISR will force exit
    __no_operation();                        // For debug only
  }
}

///中断处理函数
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = ADC12_VECTOR
__interrupt void ADC12_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12_ISR (void)
#else
#error Compiler not supported!
#endif
{
  switch (__even_in_range(ADC12IV, ADC12IV_ADC12RDYIFG))
  {
    case ADC12IV_NONE:        break;        // Vector  0:  No interrupt
    case ADC12IV_ADC12OVIFG:  break;        // Vector  2:  ADC12MEMx Overflow
    case ADC12IV_ADC12TOVIFG: break;        // Vector  4:  Conversion time overflow
    case ADC12IV_ADC12HIIFG:  break;        // Vector  6:  ADC12BHI
    case ADC12IV_ADC12LOIFG:  break;        // Vector  8:  ADC12BLO
    case ADC12IV_ADC12INIFG:  break;        // Vector 10:  ADC12BIN
    case ADC12IV_ADC12IFG0:                 // Vector 12:  ADC12MEM0 Interrupt
    case ADC12IV_ADC12IFG1:   break;        // Vector 14:  ADC12MEM1
    case ADC12IV_ADC12IFG2:   break;        // Vector 16:  ADC12MEM2
    case ADC12IV_ADC12IFG3:   break;
    case ADC12IV_ADC12IFG4:   break;        // Vector 20:  ADC12MEM4
    
    ///使用哪个ADC12MEMx存储AD结果，转换完成后就会触发响应寄存器的完成中断，标注位为ADC12IV_ADC12IFGx
    ///前提：ADC12IER0 |= ADC12IE5; //设置AD完成中断
    case ADC12IV_ADC12IFG5:   //break;        // Vector 22:  ADC12MEM5
      if (ADC12MEM5 >= 0x6B4)               // ADC12MEM = A1 > 0.5V?
        P1OUT |= BIT5;                      // P1.4 = 1
      else
        P1OUT &= ~BIT5;                     // P1.4 = 0
        __bic_SR_register_on_exit(LPM0_bits); // Exit active CPU
      break;                                // Clear CPUOFF bit from 0(SR)
    case ADC12IV_ADC12IFG6:   break;        // Vector 24:  ADC12MEM6
    case ADC12IV_ADC12IFG7:   break;        // Vector 26:  ADC12MEM7
    case ADC12IV_ADC12IFG8:   break;        // Vector 28:  ADC12MEM8
    case ADC12IV_ADC12IFG9:   break;        // Vector 30:  ADC12MEM9
    case ADC12IV_ADC12IFG10:  break;        // Vector 32:  ADC12MEM10
    case ADC12IV_ADC12IFG11:  break;        // Vector 34:  ADC12MEM11
    case ADC12IV_ADC12IFG12:  break;        // Vector 36:  ADC12MEM12     
    case ADC12IV_ADC12IFG13:  break;        // Vector 38:  ADC12MEM13
    case ADC12IV_ADC12IFG14:  break;        // Vector 40:  ADC12MEM14
    case ADC12IV_ADC12IFG15:  break;        // Vector 42:  ADC12MEM15
    case ADC12IV_ADC12IFG16:  break;        // Vector 44:  ADC12MEM16
    case ADC12IV_ADC12IFG17:  break;        // Vector 46:  ADC12MEM17
    case ADC12IV_ADC12IFG18:  break;        // Vector 48:  ADC12MEM18
    case ADC12IV_ADC12IFG19:  break;        // Vector 50:  ADC12MEM19
    case ADC12IV_ADC12IFG20:  break;        // Vector 52:  ADC12MEM20
    case ADC12IV_ADC12IFG21:  break;        // Vector 54:  ADC12MEM21
    case ADC12IV_ADC12IFG22:  break;        // Vector 56:  ADC12MEM22
    case ADC12IV_ADC12IFG23:  break;        // Vector 58:  ADC12MEM23
    case ADC12IV_ADC12IFG24:  break;        // Vector 60:  ADC12MEM24
    case ADC12IV_ADC12IFG25:  break;        // Vector 62:  ADC12MEM25
    case ADC12IV_ADC12IFG26:  break;        // Vector 64:  ADC12MEM26
    case ADC12IV_ADC12IFG27:  break;        // Vector 66:  ADC12MEM27
    case ADC12IV_ADC12IFG28:  break;        // Vector 68:  ADC12MEM28
    case ADC12IV_ADC12IFG29:  break;        // Vector 70:  ADC12MEM29
    case ADC12IV_ADC12IFG30:  break;        // Vector 72:  ADC12MEM30
    case ADC12IV_ADC12IFG31:  break;        // Vector 74:  ADC12MEM31
    case ADC12IV_ADC12RDYIFG: break;        // Vector 76:  ADC12RDY
    default: break;
  }
}