????。。。VHDL语言。。。不懂 拜托帮下忙
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那位大哥帮忙解释下这段代码。。。。非常感谢
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mult19 is
PORT
( clk : IN STD_LOGIC;
Din : IN SIGNED (9 DOWNTO 0);
Dout : OUT SIGNED (13 DOWNTO 0));
END mult19;
ARCHITECTURE a OF mult19 IS
SIGNAL s1 : SIGNED (13 DOWNTO 0);
SIGNAL s2 : SIGNED (10 DOWNTO 0);
SIGNAL s3 : SIGNED (13 DOWNTO 0);
BEGIN
P1:process(Din)
BEGIN
s1(13 DOWNTO 4)<=Din;
s1( 3 DOWNTO 0)<="0000";
s2(10 DOWNTO 1)<=Din;
s2(0)<='0';
if Din(9)='0' then
s3<=('0'&s1(13 downto 1))+("0000"&s2(10 DOWNTO 1))+("00000"&Din(9 DOWNTO 1));
else
s3<=('1'&s1(13 downto 1))+("1111"&s2(10 DOWNTO 1))+("11111"&Din(9 DOWNTO 1));
end if;
end process;
P2: PROCESS(clk)
BEGIN
if clk'event and clk='1' then
Dout<=s3;
end if;
END PROCESS;
END a;
那位大哥帮我解释下着段代码 感激不尽
[ 本帖最后由 doumaggie 于 2010-6-15 10:50 编辑 ]
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