LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY dat2bcd IS PORT(CLK:IN STD_LOGIC; DAT:IN STD_LOGIC_VECTOR(7 DOWNTO 0); BCDH,BCDL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END;
ARCHITECTURE ONE OF dat2bcd IS BEGIN PROCESS(CLK) VARIABLE X1:integer; VARIABLE X:REAL; VARIABLE A:REAL; VARIABLE B:REAL; BEGIN IF CLK='1' THEN X1:=conv_integer(DAT); X:=X1*0.0195+0.05; X:=X*10; A:=X MOD 10; X:=(X-A*10)*10; B:=X MOD 10; END IF; END PROCESS; END;
********************************************* 提示错误:Error (10327): VHDL error at dat2bcd.vhd(22): can't determine definition of operator ""*"" -- found 0 possible definitions