运行显示乱码，希望高人指点，谢谢

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运行显示乱码，希望高人指点，谢谢 [复制链接]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD1602A is
  Port ( CLK : in std_logic;  --状态机时钟信号，同时也是液晶时钟信号，其周期应该满足液晶数据的建立时间
      Reset:in std_logic;
      LCD_RS : out std_logic; --寄存器选择信号
      LCD_RW : out std_logic; --液晶读写信号
      LCD_EN : out std_logic; --液晶时钟信号
      LCD_Data : out std_logic_vector(7 downto 0));  --液晶数据信号
end LCD1602A;
architecture Behavioral of LCD1602A is
component data1_rom
port( address:in std_logic_vector(4 downto 0);
   inclock:in std_logic;
         q:out std_logic_vector(7 downto 0));
end component;
component data2_rom
port( address:in std_logic_vector(4 downto 0);
   inclock:in std_logic;
         q:out std_logic_vector(7 downto 0));
end component;
component data3_rom
port( address:in std_logic_vector(4 downto 0);
   inclock:in std_logic;
         q:out std_logic_vector(7 downto 0));
end component;
signal  CLK1 : std_logic;
signal  Clk_Out : std_logic;
signal  LCD_Clk : std_logic;
signal  m    :std_logic_vector(1 downto 0);

signal cnt4:std_logic_vector(4 downto 0);
signal cnt_rst1:std_logic;
signal cnt2:std_logic_vector(4 downto 0);
signal cnt_rst2:std_logic;
signal cnt3:std_logic_vector(4 downto 0);
signal cnt_rst3:std_logic;
signal showdata1:std_logic_vector(7 downto 0);
signal showdata2:std_logic_vector(7 downto 0);
signal showdata3:std_logic_vector(7 downto 0);

type state is (set_dlnf,set_cursor,set_dcb,set_cgram,write_cgram,set_ddram,write_LCD_Data);
  signal Current_State:state;

begin
  LCD_EN <=  Clk_Out ;
  LCD_RW <= '0' ;
process(CLK)
variable n1:integer range 0 to 19999;
begin
if rising_edge(CLK) then
if n1<19999 then
   n1:=n1+1;
else
   n1:=0;
   Clk_Out<=not Clk_Out;
end if;
end if;
end process;
LCD_Clk <= Clk_Out;
process(Clk_Out)
variable n2:integer range 0 to 499;
begin
if rising_edge(Clk_Out) then
if n2<499 then
   n2:=n2+1;
else
   n2:=0;
   Clk1<=not Clk1;
end if;
end if;
end process;
process(Clk1)
variable n3:integer range 0 to 14;
begin
if rising_edge(Clk1) then
n3:=n3+1;
if n3<=4 then
   m<="00";
   if cnt_rst1='1' then
      cnt4<=(others=>'0');
   else cnt4<=cnt4+1;end if;
elsif n3<=9 and n3>4 then
   m<="01";
   if cnt_rst2='1' then
   cnt2<=(others=>'0');
   else cnt2<=cnt2+1;end if;
else
   m<="10";
   if cnt_rst3='1' then
      cnt3<=(others=>'0');
   else cnt3<=cnt3+1;end if;
end if;
end if;
end process;
process(LCD_Clk,Reset,Current_State)
  variable cnt1: std_logic_vector(4 downto 0);
  begin
if Reset='0'then
   Current_State<=set_dlnf;
   cnt1:="11110";
   LCD_RS<='0';
elsif rising_edge(LCD_Clk)then
   Current_State <= Current_State ;
   LCD_RS <='0';
case Current_State is
   when set_dlnf=>cnt1:="00000";LCD_Data<="00000001";
      Current_State<=set_cursor;
   when set_cursor=>LCD_Data<="00111000";
      Current_State<=set_dcb;
   when set_dcb=>LCD_Data<="00001111";
      Current_State<=set_cgram;
   when set_cgram=>LCD_Data<="00000110";
      Current_State<=write_cgram;
   when write_cgram=>LCD_RS<='1';
   if m="00" then
      LCD_Data<=showdata1;
   elsif m="01"then
      LCD_Data<=showdata2;
   else
      LCD_Data<=showdata3;
   end if;
      Current_State<=set_ddram;
   when set_ddram=>
if cnt1<"11110" then
   cnt1:=cnt1+1;
else
   cnt1:="00000";
end if;
if cnt1<="01111" then
   LCD_Data<="10000000"+cnt1;--80H
else
   LCD_Data<="11000000"+cnt1-"10000";--80H
end if;
   Current_State<=write_LCD_Data;
when write_LCD_Data=>
   LCD_Data<="00000000";
   Current_State<=set_cursor;
when others => null;
end case;
  end if;
end process;
rom1:data1_rom port map(address=>cnt4,inclock=>clk,q=>showdata1);
rom2:data2_rom port map(address=>cnt2,inclock=>clk,q=>showdata2);
rom3:data3_rom port map(address=>cnt3,inclock=>clk,q=>showdata3);
end;