library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_aritch.all;
entity fenpin is
port(clk:in std_logic;
cmd:in std_logic_vector(3 downto 0);
clkout:out std_logic);
end fenpin;
architecture arch of fenpin is
signal clkt:std_logic:='0';
begin
process(clk,cmd)
variable cnt:std_logic_vector(3 downto 0):=(others=>'0');
begin
if cmd=0 then
clkt<=clk;
cnt:=(others=>'0');
elsif rising_edge(clk) then
if cnt>=cmd-1 then
clkt<=not clkt;
cnt:=(others=>'0');
else
cnt:=cnt+1;
end if;
end if;
clkout<=clkt;
end process;
end arch;