Altera参考设计-10Gbps Ethernet Loopback Reference Design

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Altera参考设计-10Gbps Ethernet Loopback Reference Design [复制链接]

The Altera® Stratix® IIGX 10 Gigabit Ethernet (10GbE) loopback reference design provides a sample design that demonstrates wire-speed operation of the 10GbE reference design described in AN516:10-Gbps Ethernet Reference Design. The loopback reference design is an SOPC Builder system that includes two instances of the custom 10GbE component from the earlier reference design and a 10 Gigabit Attachment Unit Interface (XAUI) transceiver for each. This design provides a general platform on which you can control, test, and monitor 10GbE operations.