15930168817 发表于 2024-12-9 20:17

FPGA 数据变量使用问题？

<p>input disp_data;</p>

<p>reg data_tmp;//数据缓存</p>

<p>reg sel_r;</p>

<p>&nbsp; &nbsp;&nbsp;<br />
&nbsp; &nbsp; always@(*)<br />
&nbsp; &nbsp; &nbsp; &nbsp; case(sel_r)<br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 8&#39;b0000_0001:data_tmp = disp_data;<br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 8&#39;b0000_0010:data_tmp = disp_data;<br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 8&#39;b0000_0100:data_tmp = disp_data;<br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 8&#39;b0000_1000:data_tmp = disp_data;<br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 8&#39;b0001_0000:data_tmp = disp_data;<br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 8&#39;b0010_0000:data_tmp = disp_data;<br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 8&#39;b0100_0000:data_tmp = disp_data;<br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 8&#39;b1000_0000:data_tmp = disp_data;<br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; default:data_tmp = 4&#39;b0000;<br />
&nbsp; &nbsp; &nbsp; &nbsp; endcase</p>

<p>问题：定义disp_data，下面使用时又用 disp_data，使用时放disp_data变量前面还是后面？</p>

1nnocent 发表于 2024-12-10 10:16

<p>定义信号时放前面，处理信号固定bit位时放后面表示要处理的bit范围</p>
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