夏宇闻老师书第17章一个例子仿真的问题
<p>代码如下：</p><pre>
<code>module top(data,addr,ena,read,write);
inout data;
input addr;
input ena;
input read,write;
reg ram;
assign data=(read&&ena) ? ram:8'hzz;
always @(posedge write)
begin
ram=data;
end
endmodule
</code></pre>
<p>仿真代码如下：</p>
<pre>
<code>`timescale 1 ns/ 1 ps
module top_vlg_tst();
// constants
// general purpose registers
//reg eachvec;
// test vector input registers
reg addr;
reg ram;
reg ena;
reg read;
reg write;
// wires
wire data;
// assign statements (if any)
assign data = (read && ena) ? ram:8'bzz;
top i1 (
// port map - connection between master ports and signals/registers
.addr(addr),
.data(data),
.ena(ena),
.read(read),
.write(write)
);
initial
begin
// code that executes only once
// insert code here --> begin
write=0;
forever
#5 write = ~write;
// --> end
end
initial
begin
#10 begin addr=10'h3f;read=0;ena=0;ram=8'h55; end
#10 begin read=0;ena=1;ram=8'h55;end
#10 begin read=1;ena=0;ram=8'h55;end
#10 begin read=1;ena=1;ram=8'h55;end
#10 begin read=1;ena=1;ram=8'haa;end
#10 begin read=1;ena=1;ram=8'h5a;end
#10 begin read=1;ena=1;ram=8'ha5;end
#20 $stop;
end
endmodule
</code></pre>
<p>仿真图形的一部分：</p>
<p></p>
<p>这是怎么回事？好像只读了一次，data就不更新了。然后就一直高阻。</p>
<p>请高手指教，谢谢！</p>
<p>仿真的时候data就不更新，这个是个问题，要看一下电路么</p>
Jacktang 发表于 2023-4-19 07:34
仿真的时候data就不更新，这个是个问题，要看一下电路么
<p></p>
<p>电路如下。</p>
<p>小白坐等结果<img height="48" src="https://bbs.eeworld.com.cn/static/editor/plugins/hkemoji/sticker/facebook/congra.gif" width="48" /></p>
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