modelsim仿真的问题
<p>我看夏宇闻老师的《Verilog 数字系统设计教程》第十一章例组合逻辑二一个三态数据通路控制器</p><p>代码：</p>
<pre>
<code>`define ON 1'b1
`define OFF 1'b0
module zhlj2(LinkBusSwitch,outbuf,inbuf,bus,clk);
input LinkBusSwitch;
input outbuf;
output inbuf;
input clk;
inout bus;
wire LinkBusSwitch;
wire outbuf;
reg inbuf;
wire bus;
assign bus=(LinkBusSwitch == `ON)? outbuf : 8'hzz;
always @(posedge clk)
begin
if(!LinkBusSwitch)
inbuf<=bus;
end
endmodule
</code></pre>
<p>仿真代码：</p>
<pre>
<code>`timescale 1 ns/ 1 ps
module zhlj2_vlg_tst();
// constants
// general purpose registers
//reg eachvec;
// test vector input registers
//reg treg_bus;
reg clk;
reg outbuf;
// wires
reg LinkBusSwitch;
wire bus;
wire inbuf;
// assign statements (if any)
//assign bus = treg_bus;
zhlj2 i1 (
// port map - connection between master ports and signals/registers
.LinkBusSwitch(LinkBusSwitch),
.bus(bus),
.clk(clk),
.inbuf(inbuf),
.outbuf(outbuf)
);
initial
begin
// code that executes only once
// insert code here --> begin
//begin
LinkBusSwitch=0;
clk=0;
//end
forever
#5 clk=~clk;
end
// --> end
initial
begin
#20 outbuf=15;
#20 outbuf=38;
#20 LinkBusSwitch=1;
#20 outbuf=122;
#20 outbuf=238;
#20 outbuf=72;
#20 LinkBusSwitch=0;
#20 outbuf=55;
#20 outbuf=0;
$finish;
end
endmodule
</code></pre>
<p>有一处波形不对，就是outbuf=238时，显示-18.</p>
<p>波形图如下：</p>
<p></p>
<p>请问高手，怎么回事？谢谢！</p>
<p>outbuf 改reg类型试试，一旦线与或线或，结果会变。</p><br/> <p>数据类型转换错误导致？</p>
<p>改成reg类型后，编译出错：</p>
<p></p>
<p>我把数据位宽改为9位就好了，.</p>
<p>难道把数据当成了有符号数？</p>
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