此帖出自FPGA/CPLD论坛
最新回复
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity choose is
port(clk: in std_logic;
a: in integer range 0 to 100;
b: in integer range 0 to 100;
c: in integer range 0 to 100;
d: in integer range 0 to 100;
max: in integer range 0 to 100;
min: in integer range 0 to 100);
end entity choose;
architecture behave of choose is
begin
u1: process(clk,a,b)
variable t1: integer range 0 to 100;
variable m1: integer range 0 to 100;
begin
if(a>b)then t1
详情
回复
发表于 2010-1-2 22:07
| ||
|
||
| |
|
|
| |
|
|
试试看~~~~
此帖出自FPGA/CPLD论坛
| ||
|
||
浏览过的版块 |
EEWorld Datasheet 技术支持
EEWorld订阅号
EEWorld服务号
汽车开发圈
机器人开发圈