testbench

BasaraTama

testbench [复制链接]

以下在moddelsim中仿真出错：vhdl compiler exiting；vcom failed；

哪位高手解释下

library ieee;
use ieee.std_logic_1164.all;
entity test is
end entity test;

architecture testbench of test is

component mux             
port(a,b,s: in bit;
         y: out bit);
end component mux;
signal a,b,s,y:bit;

begin
CUT:mux port map(a,b,s,y);
  process (a,b,s)
  begin
  
  if s='0' then
   y<=a;else
   y<=b;
   end if;
  end process;
  end architecture;

 

type testdata is record
a:bit;
b:bit;
s:bit;
end;
type data_array is array (nature range <>) of data_array
constant test_data:data_array:=(('0','0'),('0','1'),('1','0'),('1','1'));

process
begin
for i in test_data'range loop
a<=test_data(i).a;
b<=test_data(i).b;
s<=test_data(i).s
wait for 100ns;
end loop
wait;
end process;

chenzhufly

信息给的太少了

BasaraTama

需要什么信息？