网上也很多,这是前一段自己写的一个:
--filename : main part of digital clock system --designed by : TangQF --inputs&outputs introduction: --clk_key_deal : clk_key_deal input --reset : system reset signal --key_mode : key input of the board to alter clock's work-mode --key_add : key input of the board to add the number of
time'second or minute or hour --key_mode_out : the key output after being delt --key_add_out : the key output after being delt --date : 2010.03.14
--begin of text entity key_deal is port (key_mode,key_add,clk_key_deal : in bit; key_mode_out,key_add_out : out bit); end key_deal;
architecture ocean of key_deal is
signal k00,k01 : bit; signal k10,k11 : bit;
begin
process(clk_key_deal) begin if clk_key_deal'event and clk_key_deal='1' then k00<=k01; k01<=key_mode; key_mode_out<=k00 and k01 and key_mode;
k10<=k11; k11<=key_add; key_add_out<=k10 and k11 and key_add; end if; end process;
end ocean; --the end
[ 本帖最后由 Sea_eeworld 于 2010-6-24 11:25 编辑 ]
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