ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL = 27, /*!< # */
ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE = 29, /*!< # */
ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */
/*!<
* Private Peripheral Interrupts (PPI) for the Global Timer, per CPU
* private timer, and watchdog timer.
* * All interrupts in this group are edge triggered.
*/
ALT_INT_INTERRUPT_SCU_PARITYFAIL0 = 64, /*!< # */
ALT_INT_INTERRUPT_SCU_PARITYFAIL1 = 65, /*!< # */
ALT_INT_INTERRUPT_SCU_EV_ABORT = 66,
/*!<
* Interrupts sourced from the Snoop Control Unit (SCU).
* * All interrupts in this group are edge triggered.
*/
ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ = 67, /*!< # */
ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ = 68, /*!< # */
ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */
ALT_INT_INTERRUPT_L2_COMBINED_IRQ = 70,
/*!<
* Interrupts sourced from the L2 Cache Controller.
*
* The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache
* controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR,
* ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts.
* Consult the L2C documentation for information on these interrupts.
*
* * ECC interrupts in this group are edge triggered.
* * Other interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ = 71,
/*!<
* Interrupts sourced from the SDRAM Controller.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_EMAC0_IRQ = 147, /*!< # */
ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ = 148, /*!< # */
ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */
ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ = 150, /*!< # */
ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151,
/*!<
* Interrupts sourced from the Ethernet MAC 0 (EMAC0).
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_EMAC1_IRQ = 152, /*!< # */
ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ = 153, /*!< # */
ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */
ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ = 155, /*!< # */
ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156,
/*!<
* Interrupts sourced from the Ethernet MAC 1 (EMAC1).
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_USB0_IRQ = 157, /*!< # */
ALT_INT_INTERRUPT_USB0_ECC_CORRECTED = 158, /*!< # */
ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159,
/*!<
* Interrupts sourced from the USB OTG 0.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_USB1_IRQ = 160, /*!< # */
ALT_INT_INTERRUPT_USB1_ECC_CORRECTED = 161, /*!< # */
ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162,
/*!<
* Interrupts sourced from the USB OTG 1.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_CAN0_STS_IRQ = 163, /*!< # */
ALT_INT_INTERRUPT_CAN0_MO_IRQ = 164, /*!< # */
ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ = 165, /*!< # */
ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166,
/*!<
* Interrupts sourced from the CAN Controller 0.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_CAN1_STS_IRQ = 167, /*!< # */
ALT_INT_INTERRUPT_CAN1_MO_IRQ = 168, /*!< # */
ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ = 169, /*!< # */
ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170,
/*!<
* Interrupts sourced from the CAN Controller 1.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_SDMMC_IRQ = 171, /*!< # */
ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED = 172, /*!< # */
ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */
ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED = 174, /*!< # */
ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175,
/*!<
* Interrupts sourced from the SDMMC Controller.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_NAND_IRQ = 176, /*!< # */
ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ = 177, /*!< # */
ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */
ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ = 179, /*!< # */
ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */
ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ = 181, /*!< # */
ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182,
/*!<
* Interrupts sourced from the NAND Controller.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_QSPI_IRQ = 183, /*!< # */
ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ = 184, /*!< # */
ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185,
/*!<
* Interrupts sourced from the QSPI Controller.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */
ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */
ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */
ALT_INT_INTERRUPT_SPI3_IRQ = 189,
/*!<
* Interrupts sourced from the SPI Controllers 0 - 3.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */
ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */
ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */
ALT_INT_INTERRUPT_I2C3_IRQ = 193,
/*!<
* Interrupts sourced from the I2C Controllers 0 - 3.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_UART0 = 194, /*!< # */
ALT_INT_INTERRUPT_UART1 = 195,
/*!<
* Interrupts sourced from the UARTs 0 - 1.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */
ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */
ALT_INT_INTERRUPT_GPIO2 = 198,
/*!<
* Interrupts sourced from the GPIO 0 - 2.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */
ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */
ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */
ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202,
/*!<
* Interrupts sourced from the Timer controllers.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */
ALT_INT_INTERRUPT_WDOG1_IRQ = 204,
/*!<
* Interrupts sourced from the Watchdog Timers 0 - 1.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_CLKMGR_IRQ = 205,
/*!<
* Interrupts sourced from the Clock Manager.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206,
/*!<
* Interrupts sourced from the Clock Manager MPU Wakeup.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207,
/*!<
* Interrupts sourced from the FPGA Manager.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */
ALT_INT_INTERRUPT_NCTIIRQ1 = 209,
/*!<
* Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI.
* * All interrupts in this group are level triggered.
*/
ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ = 210, /*!< # */
ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211
/*!<
* Interrupts sourced from the On-chip RAM.
* * All interrupts in this group are level triggered.
*/