刚学VHDL，有问题向大家请教！麻烦各位帮忙看看。

jinghong21

刚学VHDL，有问题向大家请教！麻烦各位帮忙看看。 [复制链接]

请问各位，为什么我的key0_state产生下降沿的时候，dout1，dout2，dout3都可以赋值为0，可是为什么别的key_state产生下降沿，dout1，dout2，dout3却不能赋值为1,2,3,4.。。。。？请问是什么原因呢？

 

process(clk_100,key0_state,key1_state,key2_state,key3_state,
     key4_state,key5_state,key6_state,key7_state,
     key8_state,key9_state,key10_state,key11_state,
     key12_state,key13_state,key14_state,key15_state)
 variable num : integer range 0 to 3;
 begin
  if clk'event and clk='1' then
   if key0_state='1' and key0_state'event then
    if num=0 then dout1<=0; num:=num+1;
     elsif num=1 then dout2<=0; num:=num+1;
      elsif num=2 then dout3<=0; num:=num+1;
    end if;
   elsif key1_state='1' and key1_state'event then
    if num=0 then dout1<=1; num:=num+1;
     elsif num=1 then dout2<=1; num:=num+1;
      elsif num=2 then dout3<=1; num:=num+1;
    end if;
   elsif key2_state='1' and key2_state'event then
    if num=0 then dout1<=2; num:=num+1;
     elsif num=1 then dout2<=2; num:=num+1;
      elsif num=2 then dout3<=2; num:=num+1;
    end if;
   elsif key3_state='1' and key3_state'event then
    if num=0 then dout1<=3; num:=num+1;
     elsif num=1 then dout2<=3; num:=num+1;
      elsif num=2 then dout3<=3; num:=num+1;
    end if;
   elsif key4_state='1' and key4_state'event then
    if num=0 then dout1<=4; num:=num+1;
     elsif num=1 then dout2<=4; num:=num+1;
      elsif num=2 then dout3<=4; num:=num+1;
    end if;
   elsif key5_state='1' and key5_state'event then
    if num=0 then dout1<=5; num:=num+1;
     elsif num=1 then dout2<=5; num:=num+1;
      elsif num=2 then dout3<=5; num:=num+1;
    end if;
   elsif key6_state='1' and key6_state'event then
    if num=0 then dout1<=6; num:=num+1;
     elsif num=1 then dout2<=6; num:=num+1;
      elsif num=2 then dout3<=6; num:=num+1;
    end if;
   elsif key7_state='1' and key7_state'event then
    if num=0 then dout1<=7; num:=num+1;
     elsif num=1 then dout2<=7; num:=num+1;
      elsif num=2 then dout3<=7; num:=num+1;
    end if;
   elsif key8_state='1' and key8_state'event then
    if num=0 then dout1<=8; num:=num+1;
     elsif num=1 then dout2<=8; num:=num+1;
      elsif num=2 then dout3<=8; num:=num+1;
    end if;
   elsif key9_state='1' and key9_state'event then
    if num=0 then dout1<=9; num:=num+1;
     elsif num=1 then dout2<=9; num:=num+1;
      elsif num=2 then dout3<=9; num:=num+1;
    end if;
    
   elsif key10_state='1' and key10_state'event then
     confirm<='1';
     if num=1 then
      dout_send<=dout1;
      elsif num=2 then
       dout_send<=dout1*10+dout2;
       elsif num=3 then
        dout_send<=dout1*100+dout2*10+dout3;
     end if;
     num:=0;
   end if;
  end if;
 
 end process;

eeleader

  if clk'event and clk='1' then
   if key0_state='1' and key0_state'event then

上面这种写法本身就是错误的，没有按照硬件的需求来写

熊猫

太乱了，看都不想看，长传个VHDL附件嘛！

ruanxiongjie

为什么不用个case 语句呢，代码整的有点乱。

eeleader

问题解决了吗？

 

刚学VHDL，应该先搞简单一点。比如哦搞一个D触发器，分频电路等等！

给自己建立信心，然后一点一点的深入！

huzi741

代码有点乱，if语句嵌套太多了

eeleader

不知道你问题搞定没有！