美资芯片公司热招Verification Engineer

wind728 发表于 2012-3-14 14:12

某知名美资芯片公司招聘若干Verification Engineer 工作地点：上海 有意者请将中英文简历发至公司邮箱：echo.tao@talentsii.com； 任何问题均可以联系MSN：Echo.Tao@hotmail.com Senior Level Verification engineer   Network protocol and system knowledge highly desirable (Ethernet, IP, ATM, SONET, DSL, EPON/GPON)   Complete asic design/verification cycle from spec to product   Test bench and test case development using Vera/SpecmanE/SystemVerilog/Verilog/script is required   Understanding of Coverage tools   Understanding of DFT/Test vector generation/debugging   Understanding of Gate Level simulation   Knowledge of Serdes, DDR memory, SOC/CPU, interfaces is big plus   Documentation in English is highly desirable   Detail and discipline oriented   Experience in leading in verification of complex chips  Junior Level Verificaton engineer   Detail and discipline oriented, team work oriented   Understanding of ASIC/FPGA design/verification flow   Familiar with some of the  EDA tool such as Verilog/VCS, Synthesis, Timing Analysis, DFT, FPGA is required   Network protocol and system knowledge highly desirable (Ethernet, IP, ATM, SONET, DSL, EPON/GPON)   Strong skill in C/C++ UNIX scripting is desired

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美资芯片公司热招Verification Engineer