求助FPGA的各位大虾！！！
<P>紧急寻找高级FPGA的设计工程师</P><P> </P>
<P>工作地点：上海张江高科</P>
<P>要求：</P>
<P class=MsoNormal style="MARGIN: 0cm 0cm 0pt"><SPAN lang=EN-US style="FONT-SIZE: 12pt"><FONT face="Times New Roman">1</FONT></SPAN><SPAN style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: 'Times New Roman'; mso-hansi-font-family: 'Times New Roman'">、熟练应用</SPAN><SPAN lang=EN-US style="FONT-SIZE: 12pt"><FONT face="Times New Roman">VHDL</FONT></SPAN><SPAN style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: 'Times New Roman'; mso-hansi-font-family: 'Times New Roman'">或者</SPAN><SPAN lang=EN-US style="FONT-SIZE: 12pt"><FONT face="Times New Roman">Verilog HDL </FONT></SPAN><SPAN style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: 'Times New Roman'; mso-hansi-font-family: 'Times New Roman'">语言及常用</SPAN><SPAN lang=EN-US style="FONT-SIZE: 12pt"><FONT face="Times New Roman">EDA</FONT></SPAN><SPAN style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: 'Times New Roman'; mso-hansi-font-family: 'Times New Roman'">工具；</SPAN><SPAN lang=EN-US style="FONT-SIZE: 12pt"><BR><FONT face="Times New Roman">2</FONT></SPAN><SPAN style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: 'Times New Roman'; mso-hansi-font-family: 'Times New Roman'">、</SPAN><SPAN style="FONT-SIZE: 12pt; COLOR: black; FONT-FAMILY: 宋体; mso-hansi-font-family: 'Times New Roman'; mso-bidi-font-family: 宋体; mso-font-kerning: 0pt">能准确掌握<SPAN lang=EN-US>FPGA</SPAN>设计需求，进行架构设计并准确划分模块</SPAN><SPAN style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: 'Times New Roman'; mso-hansi-font-family: 'Times New Roman'">；</SPAN><SPAN lang=EN-US style="FONT-SIZE: 12pt"><BR><FONT face="Times New Roman">3</FONT></SPAN><SPAN style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: 'Times New Roman'; mso-hansi-font-family: 'Times New Roman'">、</SPAN><SPAN style="FONT-SIZE: 12pt; COLOR: black; FONT-FAMILY: 宋体; mso-hansi-font-family: 'Times New Roman'; mso-bidi-font-family: 宋体; mso-font-kerning: 0pt">从事<SPAN lang=EN-US>FPGA</SPAN>设计工作<SPAN lang=EN-US>3</SPAN>年以上，具备独立的<SPAN lang=EN-US>FPGA</SPAN>设计、仿真、上板<SPAN lang=EN-US>Debug </SPAN>能力</SPAN><SPAN style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: 'Times New Roman'; mso-hansi-font-family: 'Times New Roman'">；</SPAN><SPAN lang=EN-US style="FONT-SIZE: 12pt"><BR><FONT face="Times New Roman">4</FONT></SPAN><SPAN style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: 'Times New Roman'; mso-hansi-font-family: 'Times New Roman'">、</SPAN><SPAN style="FONT-SIZE: 12pt; COLOR: black; FONT-FAMILY: 宋体; mso-hansi-font-family: 'Times New Roman'; mso-bidi-font-family: 宋体; mso-font-kerning: 0pt">至少设计过<SPAN lang=EN-US>E1 Framer/Deframer</SPAN>、<SPAN lang=EN-US>HDLC</SPAN>控制器、以太网<SPAN lang=EN-US>MAC</SPAN>控制器、<SPAN lang=EN-US>SDH Framer/Deframer</SPAN>、<SPAN lang=EN-US>SDH Mapper/Demapper</SPAN>、<SPAN lang=EN-US>SPI4.2</SPAN>、<SPAN lang=EN-US>HiGig</SPAN>、<SPAN lang=EN-US>DDR</SPAN>、<SPAN lang=EN-US>PCI</SPAN>、<SPAN lang=EN-US>PCI-E </SPAN>等相关模块之一</SPAN><SPAN style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: 'Times New Roman'; mso-hansi-font-family: 'Times New Roman'">。</SPAN></P>
<P class=MsoNormal style="MARGIN: 0cm 0cm 0pt"><SPAN style="FONT-SIZE: 12pt; FONT-FAMILY: 宋体; mso-ascii-font-family: 'Times New Roman'; mso-hansi-font-family: 'Times New Roman'"></SPAN> </P>
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