【诚聘】Digital IC Verification Engineer
美资公司 LSI 上海研发中心高薪诚聘存储通讯领域人才，薪水待遇优厚，部分人员有出国培训机会。(部门内部推荐,成功机会更高)<BR>有意者请将中英文简历发送至：<A href="mailto:asic_tapeout@hotmail.com">asic_tapeout@hotmail.com</A><BR> <BR>Digital IC Verification Engineer<BR><BR>DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:<BR>As a member of the Read Channel team, candidate must be willing to work as an extended<BR>member of the design team. Duties will include functional verification of Storage read<BR>channel mixed-signal IP. Candidate will be expected to contribute to design and development<BR>of System Verilog based verification environment and will be responsible for verification<BR>closure of block/chip/system level functions for mixed signal based IP. Experience with<BR>System Verilog and functional coverage methodologies are required. Must be willing to<BR>follow a disciplined verification methodology and to work closely with a multi-location,<BR>international design team. Excellent teamwork and communication skills are required.<BR>PREFERRED EXPERIENCE:<BR>BSEE with 2-5+ years of design and/or verification experience required, MSEE preferred.<BR>Required knowledge and skills:<BR>- Expertise in System Verilog required<BR>- Good understanding of Digital Signal Processing<BR>- Good understanding of Analog and Digital Circuits<BR>- Very good analytical/debugging skill<BR>- Good verbal and written communication skills<BR>Desirable skills:<BR>- Knowledge of Verilog-AMS, Perl<BR>- Knowledge of verification methodologies including functional coverage and constrained<BR>random testing<BR>- Knowledge of VLSI design flows & DFT<BR>- Familiarity of high level programming language<BR>- Experience working with globally distributed team<BR>
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