关于DSP28335外扩SRAM写数据后数据跳变的问题及SRAM赋值问题

等了你半田 发表于 2024-6-26 11:44

我使用是是普中科技的28335开发板。因为要存储数组数据，所以外扩了SRAM。定义了ZONE7区域，并将数组变量指定存储到该区域。在定时器中断程序中给该变量赋值，但是在Expression中观察，赋值过后的变量值仍然会跳变，而且在memory browser中观察该值，好像并没有赋值成功。以下是相关程序及截图：

图一CpuTimer0.InterruptCount已经超过了数组的范围，然后y_out数据发生了跳变（黄色就代表发生了变化）。

图二在memory browser中观察y_out数据空间，但是并没有值被赋值进来？

另外就是，我写了给u_ff初始化赋值的语句，但是并没有赋值成功，见图三，这种怎么初始化赋值呢？

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<pre>
<code>//=============================

// ----------- time.c----------------

#pragma DATA_SECTION(y_out,"ZONE7DATA");

volatile float y_out = {0.0};

#pragma DATA_SECTION(u_ff,"ZONE7DATA");

volatile float u_ff = {

{0},

{-5.48168582231433},

{-28.0960788724069},

{-33.2755709254560},

{-28.4364523855368}

};

interrupt void TIM0_IRQn(void){

//省略其他无关代码

y_out = Pos;

CpuTimer0.InterruptCount++；

}

//==============================

// --------------28335_RAM_lnk.cmd----------------

PAGE 1 :

ZONE7B : origin = 0x201000, length = 0x0F0000 /* XINTF zone 7 */

SECTIONS

ZONE7DATA : > ZONE7B, PAGE = 1

//==============================

// -------------init_zone7.c --------------------------

void init_zone67(void)
{
EALLOW;
// Make sure the XINTF clock is enabled
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1;
EDIS;
// Configure the GPIO for XINTF with a 16-bit data bus
// This function is in DSP2833x_Xintf.c
InitXintf16Gpio();

// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = SYSCLKOUT
EALLOW;
XintfRegs.XINTCNF2.bit.XTIMCLK = 0;
// Buffer up to 3 writes
XintfRegs.XINTCNF2.bit.WRBUFF = 3;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK
XintfRegs.XINTCNF2.bit.CLKMODE = 0;

XintfRegs.XTIMING7.bit.XWRLEAD = 3;
XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
XintfRegs.XTIMING7.bit.XRDTRAIL = 3;

// don't double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 1;

// Zone will not sample XREADY signal
XintfRegs.XTIMING7.bit.USEREADY = 1;
XintfRegs.XTIMING7.bit.READYMODE = 1;

// 1,1 = x16 data bus
// 0,1 = x32 data bus
// other values are reserved
XintfRegs.XTIMING7.bit.XSIZE = 3;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
}</code></pre>

等了你半田 发表于 2024-6-26 14:03

工程中还使用了串口、spi等，但已经排除其接口与SRAM地址线数据线的复用问题

wangerxian 发表于 2024-6-26 20:31

大概率是SRAM通信时许的问题。

等了你半田 发表于 2024-9-3 15:07

wangerxian 发表于 2024-6-26 20:31
大概率是SRAM通信时许的问题。

抱歉，之前问题这个一直搁置了。以下是zone7的初始化，请问这个时序存在问题嘛？

/* 
 * init_zone7.c 
 * 
 *  Created on: 2024年6月11日 
 *      Author: Saturday 
 */

 
#include <APP/xint_zone67/init_zone67.h>

 
void init_zone7(void) 
{ 
    EALLOW; 
    // Make sure the XINTF clock is enabled 
    SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; 
    EDIS; 
    // Configure the GPIO for XINTF with a 16-bit data bus 
    // This function is in DSP2833x_Xintf.c 
    InitXintf16Gpio();

 
    // All Zones--------------------------------- 
    // Timing for all zones based on XTIMCLK = SYSCLKOUT 
    EALLOW; 
    XintfRegs.XINTCNF2.bit.XTIMCLK = 0; 
    // Buffer up to 3 writes 
    XintfRegs.XINTCNF2.bit.WRBUFF = 3; 
    // XCLKOUT is enabled 
    XintfRegs.XINTCNF2.bit.CLKOFF = 0; 
    // XCLKOUT = XTIMCLK 
    XintfRegs.XINTCNF2.bit.CLKMODE = 0;

    // Zone 7------------------------------------ 
    // When using ready, ACTIVE must be 1 or greater 
    // Lead must always be 1 or greater 
    // Zone write timing 
    XintfRegs.XTIMING7.bit.XWRLEAD = 3; 
    XintfRegs.XTIMING7.bit.XWRACTIVE = 7; 
    XintfRegs.XTIMING7.bit.XWRTRAIL = 3; 
    // Zone read timing 
    XintfRegs.XTIMING7.bit.XRDLEAD = 3; 
    XintfRegs.XTIMING7.bit.XRDACTIVE = 7; 
    XintfRegs.XTIMING7.bit.XRDTRAIL = 3;

    // don't double all Zone read/write lead/active/trail timing 
    XintfRegs.XTIMING7.bit.X2TIMING = 0;

    // Zone will not sample XREADY signal 
    XintfRegs.XTIMING7.bit.USEREADY = 0; 
    XintfRegs.XTIMING7.bit.READYMODE = 0;

    // 1,1 = x16 data bus 
    // 0,1 = x32 data bus 
    // other values are reserved 
    XintfRegs.XTIMING7.bit.XSIZE = 3; 
    EDIS; 
   //Force a pipeline flush to ensure that the write to 
   //the last register configured occurs before returning. 
   asm(" RPT #7 || NOP"); 
}

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关于DSP28335外扩SRAM写数据后数据跳变的问题及SRAM赋值问题