【兆易GD32H759I-EVAL】SDRAM测试
本帖最后由 TL-LED 于 2024-5-11 08:18 编辑<p><span style="font-size:16px;">这篇测试板卡上SDRAM存储器的读写。</span></p>
<p> </p>
<p><span style="font-size:16px;"><strong>一、硬件部分</strong></span></p>
<p> </p>
<p><span style="font-size:16px;">1.1、SDRAM电路图部分</span></p>
<p><span style="font-size:16px;">开发板扩展了一篇16MSDRAM，电路部分如下</span></p>
<p><span style="font-size:16px;"></span></p>
<p> </p>
<p><span style="font-size:16px;">1.2、SDRAM系统框架</span></p>
<p><span style="font-size:16px;"></span></p>
<p> </p>
<p><span style="font-size:16px;">1.3、SDRAM地址</span></p>
<p><span style="font-size:16px;"></span></p>
<p> </p>
<p><strong><span style="font-size:16px;">二、程序部分</span></strong></p>
<p> </p>
<p><span style="font-size:16px;">2.1、exmc_sdram.c</span></p>
<pre>
<code>/*!
\file exmc_sdram.c
\brief exmc sdram driver
\version 2024-01-05, V1.2.0, demo for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32h7xx.h"
#include "exmc/exmc_sdram.h"
/* define mode register content */
/* burst length */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000U)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001U)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002U)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0003U)
/* burst type */
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000U)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008U)
/* CAS latency */
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020U)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030U)
/* write mode */
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000U)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200U)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000U)
#define SDRAM_TIMEOUT ((uint32_t)0x0000FFFFU)
/*!
\brief software delay
\paramcount: count value
\param none
\retval none
*/
static void _delay(uint32_t count)
{
__IO uint32_t index = 0;
for(index = (100 * count); index != 0; index--) {
}
}
/*!
\brief sdram peripheral initialize
\paramsdram_device: specified SDRAM device
\param none
\retval none
*/
void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
{
exmc_sdram_parameter_struct sdram_init_struct;
exmc_sdram_timing_parameter_struct sdram_timing_init_struct;
exmc_sdram_command_parameter_struct sdram_command_init_struct;
exmc_sdram_struct_para_init(&sdram_init_struct);
uint32_t command_content = 0, bank_select;
uint32_t timeout = SDRAM_TIMEOUT;
/* enable EXMC clock */
rcu_periph_clock_enable(RCU_EXMC);
rcu_periph_clock_enable(RCU_GPIOA);
rcu_periph_clock_enable(RCU_GPIOC);
rcu_periph_clock_enable(RCU_GPIOD);
rcu_periph_clock_enable(RCU_GPIOE);
rcu_periph_clock_enable(RCU_GPIOF);
rcu_periph_clock_enable(RCU_GPIOG);
rcu_periph_clock_enable(RCU_GPIOH);
/* common GPIO configuration */
/* SDNE0(PC2),SDCKE0(PC3) pin configuration */
gpio_af_set(GPIOC, GPIO_AF_12, GPIO_PIN_2 | GPIO_PIN_3);
gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_2 | GPIO_PIN_3);
gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_2 | GPIO_PIN_3);
/* D12(PC0) pin configuration */
gpio_af_set(GPIOC, GPIO_AF_1, GPIO_PIN_0);
gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0);
gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_0);
/* D2(PD0),D3(PD1),D13(PD8),D14(PD9),D15(PD10),D0(PD14),D1(PD15) pin configuration */
gpio_af_set(GPIOD, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
gpio_mode_set(GPIOD, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 |
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
gpio_output_options_set(GPIOD, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 |
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
/* NBL0(PE0),NBL1(PE1),D4(PE7),D5(PE8),D6(PE9),D7(PE10),D8(PE11),D9(PE12),D10(PE13),D11(PE14) pin configuration */
gpio_af_set(GPIOE, GPIO_AF_12, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_7| GPIO_PIN_8 |
GPIO_PIN_9| GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |
GPIO_PIN_14);
gpio_mode_set(GPIOE, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_7| GPIO_PIN_8 |
GPIO_PIN_9| GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |
GPIO_PIN_14);
gpio_output_options_set(GPIOE, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_7| GPIO_PIN_8 |
GPIO_PIN_9| GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |
GPIO_PIN_14);
/* A0(PF0),A1(PF1),A2(PF2),A3(PF3),A4(PF4),A5(PF5),NRAS(PF11),A6(PF12),A7(PF13),A8(PF14),A9(PF15) pin configuration */
gpio_af_set(GPIOF, GPIO_AF_12, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_2| GPIO_PIN_3|
GPIO_PIN_4| GPIO_PIN_5| GPIO_PIN_11 | GPIO_PIN_12 |
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
gpio_mode_set(GPIOF, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_2| GPIO_PIN_3|
GPIO_PIN_4| GPIO_PIN_5| GPIO_PIN_11 | GPIO_PIN_12 |
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
gpio_output_options_set(GPIOF, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_2| GPIO_PIN_3|
GPIO_PIN_4| GPIO_PIN_5| GPIO_PIN_11 | GPIO_PIN_12 |
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
/* A10(PG0),A11(PG1),A12(PG2),BA0/A14(PG4),BA1/A15(PG5),SDCLK(PG8),NCAS(PG15) pin configuration */
gpio_af_set(GPIOG, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
/* SDNWE(PH5) pin configuration */
gpio_af_set(GPIOH, GPIO_AF_12, GPIO_PIN_5);
gpio_mode_set(GPIOH, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_5);
gpio_output_options_set(GPIOH, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_5);
/* specify which SDRAM to read and write */
if(EXMC_SDRAM_DEVICE0 == sdram_device) {
bank_select = EXMC_SDRAM_DEVICE0_SELECT;
} else {
bank_select = EXMC_SDRAM_DEVICE1_SELECT;
}
/* EXMC SDRAM device initialization sequence --------------------------------*/
/* step 1 : configure SDRAM timing registers --------------------------------*/
/* LMRD: 2 clock cycles */
sdram_timing_init_struct.load_mode_register_delay = 2;
/* XSRD: min = 67ns */
sdram_timing_init_struct.exit_selfrefresh_delay = 12;
/* RASD: min=42ns , max=120k (ns) */
sdram_timing_init_struct.row_address_select_delay = 8;
/* ARFD: min=60ns */
sdram_timing_init_struct.auto_refresh_delay = 11;
/* WRD:min=1 Clock cycles +6ns */
sdram_timing_init_struct.write_recovery_delay = 2;
/* RPD:min=18ns */
sdram_timing_init_struct.row_precharge_delay = 4;
/* RCD:min=18ns */
sdram_timing_init_struct.row_to_column_delay = 4;
/* step 2 : configure SDRAM control registers ---------------------------------*/
sdram_init_struct.sdram_device = sdram_device;
sdram_init_struct.column_address_width = EXMC_SDRAM_COW_ADDRESS_9;
sdram_init_struct.row_address_width = EXMC_SDRAM_ROW_ADDRESS_13;
sdram_init_struct.data_width = EXMC_SDRAM_DATABUS_WIDTH_16B;
sdram_init_struct.internal_bank_number = EXMC_SDRAM_4_INTER_BANK;
sdram_init_struct.cas_latency = EXMC_CAS_LATENCY_3_SDCLK;
sdram_init_struct.write_protection = DISABLE;
sdram_init_struct.sdclock_config = EXMC_SDCLK_PERIODS_3_CK_EXMC;
sdram_init_struct.burst_read_switch = ENABLE;
sdram_init_struct.pipeline_read_delay = EXMC_PIPELINE_DELAY_1_CK_EXMC;
sdram_init_struct.timing = &sdram_timing_init_struct;
/* EXMC SDRAM bank initialization */
exmc_sdram_init(&sdram_init_struct);
/* step 3 : configure CKE high command---------------------------------------*/
sdram_command_init_struct.command = EXMC_SDRAM_CLOCK_ENABLE;
sdram_command_init_struct.bank_select = bank_select;
sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
sdram_command_init_struct.mode_register_content = 0;
/* wait until the SDRAM controller is ready */
while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
timeout--;
}
/* send the command */
exmc_sdram_command_config(&sdram_command_init_struct);
/* step 4 : insert 10ms delay----------------------------------------------*/
_delay(100);
/* step 5 : configure precharge all command----------------------------------*/
sdram_command_init_struct.command = EXMC_SDRAM_PRECHARGE_ALL;
sdram_command_init_struct.bank_select = bank_select;
sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
sdram_command_init_struct.mode_register_content = 0;
/* wait until the SDRAM controller is ready */
timeout = SDRAM_TIMEOUT;
while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
timeout--;
}
/* send the command */
exmc_sdram_command_config(&sdram_command_init_struct);
/* step 6 : configure Auto-Refresh command-----------------------------------*/
sdram_command_init_struct.command = EXMC_SDRAM_AUTO_REFRESH;
sdram_command_init_struct.bank_select = bank_select;
sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_8_SDCLK;
sdram_command_init_struct.mode_register_content = 0;
/* wait until the SDRAM controller is ready */
timeout = SDRAM_TIMEOUT;
while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
timeout--;
}
/* send the command */
exmc_sdram_command_config(&sdram_command_init_struct);
/* step 7 : configure load mode register command-----------------------------*/
/* program mode register */
command_content = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
SDRAM_MODEREG_CAS_LATENCY_3 |
SDRAM_MODEREG_OPERATING_MODE_STANDARD |
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
sdram_command_init_struct.command = EXMC_SDRAM_LOAD_MODE_REGISTER;
sdram_command_init_struct.bank_select = bank_select;
sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
sdram_command_init_struct.mode_register_content = command_content;
/* wait until the SDRAM controller is ready */
timeout = SDRAM_TIMEOUT;
while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
timeout--;
}
/* send the command */
exmc_sdram_command_config(&sdram_command_init_struct);
/* step 8 : set the auto-refresh rate counter--------------------------------*/
/* 64ms, 8192-cycle refresh, 64ms/8192=7.81us */
/* SDCLK_Freq = SYS_Freq/2 */
/* (7.81 us * SDCLK_Freq) - 20 */
exmc_sdram_refresh_count_set(1542);
/* wait until the SDRAM controller is ready */
timeout = SDRAM_TIMEOUT;
while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
timeout--;
}
}
/*!
\brief fill the buffer with specified value
\parampbuffer: pointer to the buffer to fill data
\parambuffer_lengh: size of the buffer to fill
\paramstart_value: first data to fill in the buffer
\param none
\retval none
*/
void fill_buffer(uint8_t *pbuffer, uint16_t buffer_lengh, uint16_t start_value)
{
uint16_t index = 0;
/* fill the buffer with specified values */
for(index = 0; index < buffer_lengh; index++) {
pbuffer = (uint8_t)(index + start_value);
}
}
/*!
\brief write a byte buffer(data is 8 bits) to the EXMC SDRAM memory
\paramsdram_device: specify which a SDRAM memory block is written
\parampbuffer: pointer to buffer
\paramwrite_addr: SDRAM memory internal address from which the data will be written
\parambyte_count_to_write: number of bytes to write
\param none
\retval none
*/
void sdram_writebuffer_8(uint32_t sdram_device, uint8_t *pbuffer, uint32_t write_addr, uint32_t byte_count_to_write)
{
uint32_t temp_addr;
/* select the base address according to EXMC_Bank */
if(sdram_device == EXMC_SDRAM_DEVICE0) {
temp_addr = SDRAM_DEVICE0_ADDR;
} else {
temp_addr = SDRAM_DEVICE1_ADDR;
}
/* while there is data to write */
for(; byte_count_to_write != 0; byte_count_to_write--) {
/* transfer data to the memory */
*(uint8_t *)(temp_addr + write_addr) = *pbuffer++;
/* increment the address */
write_addr += 1;
}
}
/*!
\brief read a block of 8-bit data from the EXMC SDRAM memory
\paramsdram_device: specify which a SDRAM memory block is written
\parampbuffer: pointer to buffer
\paramread_addr: SDRAM memory internal address to read from
\parambyte_count_to_read: number of bytes to read
\param none
\retval none
*/
void sdram_readbuffer_8(uint32_t sdram_device, uint8_t *pbuffer, uint32_t read_addr, uint32_t byte_count_to_read)
{
uint32_t temp_addr;
/* select the base address according to EXMC_Bank */
if(sdram_device == EXMC_SDRAM_DEVICE0) {
temp_addr = SDRAM_DEVICE0_ADDR;
} else {
temp_addr = SDRAM_DEVICE1_ADDR;
}
/* while there is data to read */
for(; byte_count_to_read != 0; byte_count_to_read--) {
/* read a byte from the memory */
*pbuffer++ = *(uint8_t *)(temp_addr + read_addr);
/* increment the address */
read_addr += 1;
}
}
</code></pre>
<p> </p>
<p><span style="font-size:16px;">2.2、exmc_sdram.h</span></p>
<pre>
<code>/*!
\file exmc_sdram.c
\brief exmc sdram driver
\version 2024-01-05, V1.2.0, demo for GD32H7xx
*/
/*
Copyright (c) 2024, GigaDevice Semiconductor Inc.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#include "gd32h7xx.h"
#include "exmc/exmc_sdram.h"
/* define mode register content */
/* burst length */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000U)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001U)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002U)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0003U)
/* burst type */
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000U)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008U)
/* CAS latency */
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020U)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030U)
/* write mode */
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000U)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200U)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000U)
#define SDRAM_TIMEOUT ((uint32_t)0x0000FFFFU)
/*!
\brief software delay
\paramcount: count value
\param none
\retval none
*/
static void _delay(uint32_t count)
{
__IO uint32_t index = 0;
for(index = (100 * count); index != 0; index--) {
}
}
/*!
\brief sdram peripheral initialize
\paramsdram_device: specified SDRAM device
\param none
\retval none
*/
void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device)
{
exmc_sdram_parameter_struct sdram_init_struct;
exmc_sdram_timing_parameter_struct sdram_timing_init_struct;
exmc_sdram_command_parameter_struct sdram_command_init_struct;
exmc_sdram_struct_para_init(&sdram_init_struct);
uint32_t command_content = 0, bank_select;
uint32_t timeout = SDRAM_TIMEOUT;
/* enable EXMC clock */
rcu_periph_clock_enable(RCU_EXMC);
rcu_periph_clock_enable(RCU_GPIOA);
rcu_periph_clock_enable(RCU_GPIOC);
rcu_periph_clock_enable(RCU_GPIOD);
rcu_periph_clock_enable(RCU_GPIOE);
rcu_periph_clock_enable(RCU_GPIOF);
rcu_periph_clock_enable(RCU_GPIOG);
rcu_periph_clock_enable(RCU_GPIOH);
/* common GPIO configuration */
/* SDNE0(PC2),SDCKE0(PC3) pin configuration */
gpio_af_set(GPIOC, GPIO_AF_12, GPIO_PIN_2 | GPIO_PIN_3);
gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_2 | GPIO_PIN_3);
gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_2 | GPIO_PIN_3);
/* D12(PC0) pin configuration */
gpio_af_set(GPIOC, GPIO_AF_1, GPIO_PIN_0);
gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0);
gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_0);
/* D2(PD0),D3(PD1),D13(PD8),D14(PD9),D15(PD10),D0(PD14),D1(PD15) pin configuration */
gpio_af_set(GPIOD, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 |
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
gpio_mode_set(GPIOD, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 |
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
gpio_output_options_set(GPIOD, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 |
GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15);
/* NBL0(PE0),NBL1(PE1),D4(PE7),D5(PE8),D6(PE9),D7(PE10),D8(PE11),D9(PE12),D10(PE13),D11(PE14) pin configuration */
gpio_af_set(GPIOE, GPIO_AF_12, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_7| GPIO_PIN_8 |
GPIO_PIN_9| GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |
GPIO_PIN_14);
gpio_mode_set(GPIOE, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_7| GPIO_PIN_8 |
GPIO_PIN_9| GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |
GPIO_PIN_14);
gpio_output_options_set(GPIOE, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_7| GPIO_PIN_8 |
GPIO_PIN_9| GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |
GPIO_PIN_14);
/* A0(PF0),A1(PF1),A2(PF2),A3(PF3),A4(PF4),A5(PF5),NRAS(PF11),A6(PF12),A7(PF13),A8(PF14),A9(PF15) pin configuration */
gpio_af_set(GPIOF, GPIO_AF_12, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_2| GPIO_PIN_3|
GPIO_PIN_4| GPIO_PIN_5| GPIO_PIN_11 | GPIO_PIN_12 |
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
gpio_mode_set(GPIOF, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_2| GPIO_PIN_3|
GPIO_PIN_4| GPIO_PIN_5| GPIO_PIN_11 | GPIO_PIN_12 |
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
gpio_output_options_set(GPIOF, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_0| GPIO_PIN_1| GPIO_PIN_2| GPIO_PIN_3|
GPIO_PIN_4| GPIO_PIN_5| GPIO_PIN_11 | GPIO_PIN_12 |
GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15);
/* A10(PG0),A11(PG1),A12(PG2),BA0/A14(PG4),BA1/A15(PG5),SDCLK(PG8),NCAS(PG15) pin configuration */
gpio_af_set(GPIOG, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 |
GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15);
/* SDNWE(PH5) pin configuration */
gpio_af_set(GPIOH, GPIO_AF_12, GPIO_PIN_5);
gpio_mode_set(GPIOH, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_5);
gpio_output_options_set(GPIOH, GPIO_OTYPE_PP, GPIO_OSPEED_85MHZ, GPIO_PIN_5);
/* specify which SDRAM to read and write */
if(EXMC_SDRAM_DEVICE0 == sdram_device) {
bank_select = EXMC_SDRAM_DEVICE0_SELECT;
} else {
bank_select = EXMC_SDRAM_DEVICE1_SELECT;
}
/* EXMC SDRAM device initialization sequence --------------------------------*/
/* step 1 : configure SDRAM timing registers --------------------------------*/
/* LMRD: 2 clock cycles */
sdram_timing_init_struct.load_mode_register_delay = 2;
/* XSRD: min = 67ns */
sdram_timing_init_struct.exit_selfrefresh_delay = 12;
/* RASD: min=42ns , max=120k (ns) */
sdram_timing_init_struct.row_address_select_delay = 8;
/* ARFD: min=60ns */
sdram_timing_init_struct.auto_refresh_delay = 11;
/* WRD:min=1 Clock cycles +6ns */
sdram_timing_init_struct.write_recovery_delay = 2;
/* RPD:min=18ns */
sdram_timing_init_struct.row_precharge_delay = 4;
/* RCD:min=18ns */
sdram_timing_init_struct.row_to_column_delay = 4;
/* step 2 : configure SDRAM control registers ---------------------------------*/
sdram_init_struct.sdram_device = sdram_device;
sdram_init_struct.column_address_width = EXMC_SDRAM_COW_ADDRESS_9;
sdram_init_struct.row_address_width = EXMC_SDRAM_ROW_ADDRESS_13;
sdram_init_struct.data_width = EXMC_SDRAM_DATABUS_WIDTH_16B;
sdram_init_struct.internal_bank_number = EXMC_SDRAM_4_INTER_BANK;
sdram_init_struct.cas_latency = EXMC_CAS_LATENCY_3_SDCLK;
sdram_init_struct.write_protection = DISABLE;
sdram_init_struct.sdclock_config = EXMC_SDCLK_PERIODS_3_CK_EXMC;
sdram_init_struct.burst_read_switch = ENABLE;
sdram_init_struct.pipeline_read_delay = EXMC_PIPELINE_DELAY_1_CK_EXMC;
sdram_init_struct.timing = &sdram_timing_init_struct;
/* EXMC SDRAM bank initialization */
exmc_sdram_init(&sdram_init_struct);
/* step 3 : configure CKE high command---------------------------------------*/
sdram_command_init_struct.command = EXMC_SDRAM_CLOCK_ENABLE;
sdram_command_init_struct.bank_select = bank_select;
sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
sdram_command_init_struct.mode_register_content = 0;
/* wait until the SDRAM controller is ready */
while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
timeout--;
}
/* send the command */
exmc_sdram_command_config(&sdram_command_init_struct);
/* step 4 : insert 10ms delay----------------------------------------------*/
_delay(100);
/* step 5 : configure precharge all command----------------------------------*/
sdram_command_init_struct.command = EXMC_SDRAM_PRECHARGE_ALL;
sdram_command_init_struct.bank_select = bank_select;
sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
sdram_command_init_struct.mode_register_content = 0;
/* wait until the SDRAM controller is ready */
timeout = SDRAM_TIMEOUT;
while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
timeout--;
}
/* send the command */
exmc_sdram_command_config(&sdram_command_init_struct);
/* step 6 : configure Auto-Refresh command-----------------------------------*/
sdram_command_init_struct.command = EXMC_SDRAM_AUTO_REFRESH;
sdram_command_init_struct.bank_select = bank_select;
sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_8_SDCLK;
sdram_command_init_struct.mode_register_content = 0;
/* wait until the SDRAM controller is ready */
timeout = SDRAM_TIMEOUT;
while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
timeout--;
}
/* send the command */
exmc_sdram_command_config(&sdram_command_init_struct);
/* step 7 : configure load mode register command-----------------------------*/
/* program mode register */
command_content = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |
SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
SDRAM_MODEREG_CAS_LATENCY_3 |
SDRAM_MODEREG_OPERATING_MODE_STANDARD |
SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
sdram_command_init_struct.command = EXMC_SDRAM_LOAD_MODE_REGISTER;
sdram_command_init_struct.bank_select = bank_select;
sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK;
sdram_command_init_struct.mode_register_content = command_content;
/* wait until the SDRAM controller is ready */
timeout = SDRAM_TIMEOUT;
while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
timeout--;
}
/* send the command */
exmc_sdram_command_config(&sdram_command_init_struct);
/* step 8 : set the auto-refresh rate counter--------------------------------*/
/* 64ms, 8192-cycle refresh, 64ms/8192=7.81us */
/* SDCLK_Freq = SYS_Freq/2 */
/* (7.81 us * SDCLK_Freq) - 20 */
exmc_sdram_refresh_count_set(1542);
/* wait until the SDRAM controller is ready */
timeout = SDRAM_TIMEOUT;
while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)) {
timeout--;
}
}
/*!
\brief fill the buffer with specified value
\parampbuffer: pointer to the buffer to fill data
\parambuffer_lengh: size of the buffer to fill
\paramstart_value: first data to fill in the buffer
\param none
\retval none
*/
void fill_buffer(uint8_t *pbuffer, uint16_t buffer_lengh, uint16_t start_value)
{
uint16_t index = 0;
/* fill the buffer with specified values */
for(index = 0; index < buffer_lengh; index++) {
pbuffer = (uint8_t)(index + start_value);
}
}
/*!
\brief write a byte buffer(data is 8 bits) to the EXMC SDRAM memory
\paramsdram_device: specify which a SDRAM memory block is written
\parampbuffer: pointer to buffer
\paramwrite_addr: SDRAM memory internal address from which the data will be written
\parambyte_count_to_write: number of bytes to write
\param none
\retval none
*/
void sdram_writebuffer_8(uint32_t sdram_device, uint8_t *pbuffer, uint32_t write_addr, uint32_t byte_count_to_write)
{
uint32_t temp_addr;
/* select the base address according to EXMC_Bank */
if(sdram_device == EXMC_SDRAM_DEVICE0) {
temp_addr = SDRAM_DEVICE0_ADDR;
} else {
temp_addr = SDRAM_DEVICE1_ADDR;
}
/* while there is data to write */
for(; byte_count_to_write != 0; byte_count_to_write--) {
/* transfer data to the memory */
*(uint8_t *)(temp_addr + write_addr) = *pbuffer++;
/* increment the address */
write_addr += 1;
}
}
/*!
\brief read a block of 8-bit data from the EXMC SDRAM memory
\paramsdram_device: specify which a SDRAM memory block is written
\parampbuffer: pointer to buffer
\paramread_addr: SDRAM memory internal address to read from
\parambyte_count_to_read: number of bytes to read
\param none
\retval none
*/
void sdram_readbuffer_8(uint32_t sdram_device, uint8_t *pbuffer, uint32_t read_addr, uint32_t byte_count_to_read)
{
uint32_t temp_addr;
/* select the base address according to EXMC_Bank */
if(sdram_device == EXMC_SDRAM_DEVICE0) {
temp_addr = SDRAM_DEVICE0_ADDR;
} else {
temp_addr = SDRAM_DEVICE1_ADDR;
}
/* while there is data to read */
for(; byte_count_to_read != 0; byte_count_to_read--) {
/* read a byte from the memory */
*pbuffer++ = *(uint8_t *)(temp_addr + read_addr);
/* increment the address */
read_addr += 1;
}
}
</code></pre>
<p> </p>
<p><span style="font-size:16px;">2.3、main.c</span></p>
<pre>
<code>#include "main.h"
uint16_t sdram_testdat __attribute__((at(0XC0000000)));
void cache_enable(void);
int main(void)
{
uint32_t sd=0;
cache_enable();
systick_config();
init_usart(115200);
init_led();
exmc_synchronous_dynamic_ram_init(EXMC_SDRAM_DEVICE0);
printf("\r\n SDRAM写入数据!\r\n ");
for(sd=0;sd<1000;sd++)
{
sdram_testdat=sd;
printf("%d ",sd);
if((sd%50)==0)
{
printf("\r\n");
}
}
printf("\r\n");
printf("\r\n SDRAM读出数据!\r\n ");
for(sd=0;sd<1000;sd++)
{
//sdram_testdat=sd;
printf("%d ",sdram_testdat);
if((sd%50)==0)
{
printf("\r\n");
}
}
printf("\r\n");
while(1)
{
led1_tog();
delay_1ms(500);
}
}
void cache_enable(void)
{
/* enable i-cache */
SCB_EnableICache();
/* enable d-cache */
SCB_EnableDCache();
}</code></pre>
<p> </p>
<p><span style="font-size:16px;"><strong>三、程序运行</strong></span></p>
<p> </p>
<p><span style="font-size: 16px;">下载程序运行后，串口输出SDRAM读写测试结果。</span></p>
<p><span style="font-size: 16px;"></span></p>
<p> </p>
<p>官方的例程挺好上手的吧。</p>
lugl4313820 发表于 2024-5-11 11:28
官方的例程挺好上手的吧。
<p>这个还可以<img height="48" src="https://bbs.eeworld.com.cn/static/editor/plugins/hkemoji/sticker/facebook/loveliness.gif" width="48" /></p>
lugl4313820 发表于 2024-5-11 11:28
官方的例程挺好上手的吧。
<p>例程好难</p>
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