【中科亿海微EQ6HL45开发平台测评体验】+ 使用新兴数字电路设计语言Chisel开发FPGA
<section id="chisel-windows-11"><h1>使用新兴数字电路设计语言Chisel开发EHiWAY-FPGA</h1>
<h2> </h2>
<h2>1.1. Chisel安装（Windows 11）<a href="http://www.summerdawn.top:7080/chisel-book/chisel-book_Notes.html#chisel-windows-11" title="Permalink to this heading"></a></h2>
<blockquote>
<ol>
<li>
<dl>
<dt>确认安装有java8。</dt>
<dd>
<dl>
<dt>java -version</dt>
<dd>
<p>java version “1.8.0_291”</p>
</dd>
</dl>
</dd>
</dl>
</li>
<li>
<p>下载sbt-1.8.0.zip，scala3-3.2.1.zip。</p>
</li>
<li>
<p>解压缩。</p>
</li>
<li>
<dl>
<dt>添加到PATH环境变量。</dt>
<dd>
<p>$env:PATH+=”;G:DevToolssbtbin;G:DevToolsscala3-3.2.1bin”</p>
<dl>
<dt>sbt -version</dt>
<dd>
<p>sbt version in this project: 1.8.0 sbt script version: 1.8.0</p>
</dd>
<dt>scala -version</dt>
<dd>
<p>Scala code runner version 3.2.1 – Copyright 2002-2022, LAMP/EPFL</p>
</dd>
</dl>
</dd>
</dl>
</li>
</ol>
</blockquote>
</section>
<section id="helloled">
<h2>1.2. HelloLED例程<a href="http://www.summerdawn.top:7080/chisel-book/chisel-book_Notes.html#helloled" title="Permalink to this heading"></a></h2>
<ol>
<li>
<p>输入chisel源代码 HelloLED.scala</p>
<blockquote>
<pre style="background:#555; padding:10px; color:#ddd !important;">
import chisel3._
class HelloLED extends Module {
val io = IO(new Bundle {
val led = Output(UInt(1.W))
})
val CNT_MAX = (50000000 / 2 -1).U;
val cntReg = RegInit(0.U(32.W))
val blkReg = RegInit(0.U(1.W))
cntReg := cntReg + 1.U
when(cntReg === CNT_MAX) {
cntReg := 0.U
blkReg := ~ blkReg
}
io.led := blkReg
}
object HelloLED extends App {
(new chisel3.stage.ChiselStage).emitVerilog(new HelloLED())
}
</pre>
<p>PS1: 由于FPGA开发板上的LED是低电平点亮，因此blkReg初始化值应改为1’b1，即</p>
<pre style="background:#555; padding:10px; color:#ddd !important;">
val blkReg = RegInit(1.U(1.W))
</pre>
</blockquote>
</li>
<li>
<p>输入项目顶端文件HelloLED_top.v</p>
<blockquote>
<p>同样由于FPGA开发板的按键是按下为低电平，为了保持scala代码简洁性，添加top模块的verilog源代码，将信号反相，此时HelloLED.scala则无需修改LED的初始电平，即无需按照前述的PS1中的改动。</p>
<pre style="background:#555; padding:10px; color:#ddd !important;">
module HelloLED_top(
input sys_clk,
input sys_rstn,
output led);
wire h_io_led;
wire res;
assign led = ~h_io_led;
assign res = ~sys_rstn;
HelloLED u_HelloLED (
.clock(sys_clk),
.reset(res),
.led( h_io_led )
);
endmodule
</pre>
</blockquote>
</li>
<li>
<p>输入chisel的构建文件 build.sbt</p>
<blockquote>
<pre style="background:#555; padding:10px; color:#ddd !important;">
scalaVersion := "2.12.13"
scalacOptions ++= Seq(
"-feature",
"-language:reflectiveCalls",
)
// Chisel 3.5
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.3" cross CrossVersion.full)
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.5.3"
libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.3"
</pre>
</blockquote>
</li>
<li>
<p>构建生成verilog</p>
<blockquote>
<p>sbt run</p>
<p>即可生成的HelloLED.v。</p>
</blockquote>
<p> </p>
</li>
</ol>
</section>
<ol>
<li>
<p>将Chisel生成的HelloLED.v，以及我们手动输入的HelloLED_top.v，添加到EHiWAY-FPGA项目中。</p>
</li>
<li>
<p>综合、编译，完成FPGA项目的构建流程后，生成码流文件并下载</p>
</li>
<li>
<p>运行效果：</p>
</li>
</ol>
<p></p>
感谢分享，期待精彩继续！
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