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[原创] 表格形式的Cortex-M0、M3、M4指令对比

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发表于 2018-8-8 16:27:20 | 显示全部楼层 |阅读模式

表格形式的Cortex-M0、M3、M4指令对比

M0
M3
M4
Bits
Type
Mnemonic
Operands
Brief description
Flags
M0




ADCS
{Rd,}Rn,Rm
Add with Carry
N,Z,C,V
=
M3
M4
16
16/32
ADC, ADCS
{Rd,} Rn, Op2
Add with Carry 带进位加法
N,Z,C,V
M0




ADD{S}
{Rd,}Rn,<Rm|#imm>
Add
N,Z,C,V
=
M3
M4
16

ADD, ADDS
{Rd,} Rn, Op2
Add
N,Z,C,V

M3
M4
32

ADD, ADDW
{Rd,} Rn, #imm12
Add 寬加法
N,Z,C,V
M0
M3
M4

Memory
ADR
Rd,label
PC-relative Address to Register  
-
M0




ANDS
{Rd,}Rn,Rm
Bitwise AND
N,Z
=
M3
M4
16
16/32
AND, ANDS
{Rd,} Rn, Op2
Logical AND
N,Z,C
M0



Shift
ASRS
{Rd,}Rm,<Rs|#imm>
Arithmetic Shift Right 算术右移
N,Z,C
=
M3
M4
16
16/32
ASR, ASRS
Rd, Rm, <Rs|#n>
Arithmetic Shift Right 算術右移
N,Z,C
M0
M3
M4
16
16/32
B{cc}
label
Branch {conditionally}
-

M3
M4
32

BFC
Rd, #lsb, #width
Bit Field Clear 位段清零
-

M3
M4
32

BFI
Rd, Rn, #lsb, #width
Bit Field Insert 位段插入
-
M0




BICS
{Rd,}Rn,Rm
Bit Clear
N,Z
=
M3
M4
16

BIC, BICS
{Rd,} Rn, Op2
Bit Clear 按位清零
N,Z,C
M0
M3
M4
16
BKPT
#imm
Breakpoint
-
M0
M3
M4
16
16/32
BL
label
Branch with Link
-
M0
M3
M4

Branch
BLX
Rm
Branch indirect with Link
-
M0
M3
M4

Branch
BX
Rm
Branch indirect  
-

M3
M4
16

CBNZ
Rn,label
Compare and Branch if Non Zero
-

M3
M4
16

CBZ
Rn,label
Compare and Branch if Zero
-

M3
M4
32

CLREX
-
Clear Exclusive
-

M3
M4
32

CLZ
Rd,Rm
Count Leading Zeros 計算前導零的數目
-
M0
M3
M4
16
16/32
CMN
Rn,Rm
Compare Negative
N,Z,C,V
M0
M3
M4
16
16/32
CMP
Rn,<Rm|#imm>
Compare
N,Z,C,V
M0
M3
M4
16
CPSID
i
Change Processor State, Disable Interrupts
-
M0
M3
M4
16
CPSIE
i
Change Processor State, Enable Interrupts
-
M0
M3
M4
32
DMB
-
Data Memory Barrier
-
M0
M3
M4
32
DSB
-
Data Synchronization Barrier
-
M0




EORS
{Rd,}Rn,Rm
Exclusive OR
N,Z
=
M3
M4
16
16/32
EOR, EORS
{Rd,} Rn, Op2
Exclusive OR
N,Z,C
M0
M3
M4
32
ISB
-
Instruction Synchronization Barrier
-

M3
M4
16

IT
-
If-Then condition block
-
M0
M3
M4
32
Memory
LDM
Rn{!},reglist
Load Multiple registers, increment after
-
+
M3
M4
16
Memory
LDMDB, LDMEA
Rn{!},reglist
Load Multiple registers, decrement before

+
M3
M4

Memory
LDMFD, LDMIA
Rn{!},reglist
Load Multiple registers, increment after

M0



Memory
LDR
Rt,label
Load Register from PC-relative address
-
M0
M3
M4
16
16/32
LDR
Rt,[Rn,<Rm|#imm>]
Load Register with word
-
=

M4

Memory
LDR
Rt, [Rn, #offset]
Load Register with word
-
M0



Memory
LDRB
Rt,[Rn,<Rm|#imm>]
Load Register with byte
-
=
M3
M4
16
16/32
LDRB, LDRBT
Rt, [Rn, #offset]
Load Register with byte
-

M3
M4
32
Memory
LDRD
Rt,Rt2,[Rn,#offset]
Load Register with two bytes
-

M3
M4
32
Memory
LDREX
Rt,[Rn,#offset]
Load Register Exclusive
-

M3
M4
32
Memory
LDREXB
Rt,[Rn]
Load Register Exclusive with Byte
-

M3
M4
32
Memory
LDREXH
Rt,[Rn]
Load Register Exclusive with Halfword
-
M0



Memory
LDRH
Rt,[Rn,<Rm|#imm>]
Load Register with halfword
-
=
M3
M4
16
16/32
LDRH, LDRHT
Rt, [Rn, #offset]
Load Register with halfword
-
M0



Memory
LDRSB
Rt,[Rn,<Rm|#imm>]
Load Register with signed byte
-
=
M3
M4
16
Memory
LDRSB, LDRSBT
Rt, [Rn, #offset]
Load Register with signed byte
-
M0



Memory
LDRSH
Rt,[Rn,<Rm|#imm>]
Load Register with signed halfword
-
=
M3
M4
16
16/32
LDRSH, LDRSHT
Rt, [Rn, #offset]
Load Register with signed halfword
-

M3
M4

Memory
LDRT
Rt, [Rn, #offset]
Load Register with word
-
M0
M3
M4
16
16/32
LSLS
{Rd,}Rn,<Rs|#imm>
Logical Shift Left
N,Z,C
M0
M3
M4
16
16/32
LSRS
{Rd,}Rn,<Rs|#imm>
Logical Shift Right
N,Z,C

M3
M4
32

MLA
Rd, Rn, Rm, Ra
Multiply with Accumulate, 32-bit result 乘加
-

M3
M4
32

MLS
Rd, Rn, Rm, Ra
Multiply and Subtract, 32-bit result 乘減
-
M0




MOV{S}
Rd,Rm
Move
N,Z
=
M3
M4
16

MOV, MOVS
Rd, Op2
Move
N,Z,C

M3
M4
32

MOVT
Rd, #imm16
Move Top 把16位立即數放到高8位
-

M3
M4
32

MOVW, MOV
Rd, #imm16
Move 16-bit constant 把16位立即數放到低8位
N,Z,C
M0
M3
M4
32
MRS
Rd,spec_reg
Move to general register from special register
-
M0
M3
M4
32
MSR
spec_reg,Rm
Move to special register from general register  
N,Z,C,V
M0
M3
M4
16
16/32
MUL, MULS
Rd,Rn,Rm
Multiply, 32-bit result
N,Z
M0




MVNS
Rd,Rm
Bitwise NOT
N,Z
=
M3
M4
16
16/32
MVN, MVNS
Rd, Op2
Bitwise NOT 加載一個數的NOT值
N,Z,C
M0
M3
M4
16
NOP
-
No Operation
-

M3
M4
32

ORN, ORNS
{Rd,} Rn, Op2
Logical OR NOT
N,Z,C
M0




ORRS
{Rd,}Rn,Rm
Logical OR
N,Z
=
M3
M4
16
16/32
ORR, ORRS
{Rd,} Rn, Op2
Logical OR
N,Z,C


M4


PKHTB, PKHBT
{Rd,} Rn, Rm, Op2
Pack Halfword
-
M0
M3
M4
16
16/32
POP
reglist
Pop registers from stack
-
M0
M3
M4
16
16/32
PUSH
reglist
Push registers onto stack
-


M4


QADD
{Rd,} Rn, Rm
Saturating double and Add
Q


M4


QADD16
{Rd,} Rn, Rm
Saturating Add 16
-


M4


QADD8
{Rd,} Rn, Rm
Saturating Add 8
-


M4


QASX
{Rd,} Rn, Rm
Saturating Add and Subtract with Exchange
-


M4


QDADD
{Rd,} Rn, Rm
Saturating Add
Q


M4


QDSUB
{Rd,} Rn, Rm
Saturating double and Subtract
Q


M4


QSAX
{Rd,} Rn, Rm
Saturating Subtract and Add with Exchange
-


M4


QSUB
{Rd,} Rn, Rm
Saturating Subtract
Q


M4


QSUB16
{Rd,} Rn, Rm
Saturating Subtract 16
-


M4


QSUB8
{Rd,} Rn, Rm
Saturating Subtract 8
-

M3
M4
32

RBIT
Rd, Rn
Reverse Bits 位反轉
-
M0
M3
M4
16
16/32
REV
Rd,Rm
Byte-Reverse word 字節反轉
-
M0
M3
M4
32

REV16
Rd,Rm
Byte-Reverse packed halfwords
-
M0
M3
M4
16

REVSH
Rd,Rm
Byte-Reverse signed halfword
-
M0



Shift
RORS
{Rd,}Rn,Rs
Rotate Right
N,Z,C
=
M3
M4
16
16/32
ROR, RORS
Rd, Rm, <Rs|#n>
Rotate Right
N,Z,C

M3
M4
32
Shift
RRX, RRXS
Rd, Rm
Rotate Right with Extend
N,Z,C
M0



Shift
RSBS
{Rd,}Rn,#0
Reverse Subtract
N,Z,C,V
=
M3
M4

Shift
RSB, RSBS
{Rd,} Rn, Op2
Reverse Subtract
N,Z,C,V


M4


SADD16
{Rd,} Rn, Rm
Signed Add 16
GE


M4


SDADD8
{Rd,} Rn, Rm
Signed Add 8
GE


M4


SASX
{Rd,} Rn, Rm
Signed Add and Subtract with Exchange
GE
M0
M3
M4
16
16/32
SBC, SBCS
{Rd,}Rn,Rm
Subtract with Carry
N,Z,C,V

M3
M4
32

SBFX
Rd, Rn, #lsb, #width
Signed Bit Field Extract
-

M3
M4
32

SDIV
{Rd,} Rn, Rm
Signed Divide
-
M0
M3
M4
32
SEV
-
Send Event
-


M4


SHADD16
{Rd,} Rn, Rm
Signed Halving Add 16
-


M4


SHADD8
{Rd,} Rn, Rm
Signed Halving Add 8
-


M4


SHASX
{Rd,} Rn, Rm
Signed Halving Add and Subtract with Exchange
-


M4


SHSAX
{Rd,} Rn, Rm
Signed Halving Subtract and Add with Exchange
-


M4


SHSUB16
{Rd,} Rn, Rm
Signed Halving Subtract 16
-


M4


SHSUB8
{Rd,} Rn, Rm
Signed Halving Subtract 8
-


M4


SMLABB, SMLABT,
SMLATB, SMLATT
Rd, Rn, Rm, Ra
Signed Multiply Accumulate Long (halfwords)
Q


M4


SMLAD, SMLADX
Rd, Rn, Rm, Ra
Signed Multiply Accumulate Dual
Q

M3
M4
32

SMLAL
RdLo, RdHi, Rn, Rm
Signed Multiply with Accumulate (32 x 32 + 64),64-bit result



M4


SMLALBB, SMLALBT,
SMLALTB, SMLALTT
RdLo, RdHi, Rn, Rm
Signed Multiply Accumulate Long, halfwords
-


M4


SMLALD, SMLALDX
RdLo, RdHi, Rn, Rm
Signed Multiply Accumulate Long Dual
-


M4


SMLAWB, SMLAWT
Rd, Rn, Rm, Ra
Signed Multiply Accumulate, word by halfword
Q


M4


SMLSD
Rd, Rn, Rm, Ra
Signed Multiply Subtract Dual
Q


M4


SMLSLD
RdLo, RdHi, Rn, Rm
Signed Multiply Subtract Long Dual



M4


SMMLA
Rd, Rn, Rm, Ra
Signed Most significant word Multiply Accumulate
-


M4


SMMLS, SMMLR
Rd, Rn, Rm, Ra
Signed Most significant word Multiply Subtract
-


M4


SMMUL, SMMULR
{Rd,} Rn, Rm
Signed Most significant word Multiply
-


M4


SMUAD
{Rd,} Rn, Rm
Signed dual Multiply Add
Q


M4


SMULBB, SMULBT
SMULTB, SMULTT
{Rd,} Rn, Rm
Signed Multiply (halfwords)
-

M3
M4
32

SMULL
RdLo, RdHi, Rn, Rm
Signed Multiply (32 x 32), 64-bit result
-


M4


SMULWB, SMULWT
{Rd,} Rn, Rm
Signed Multiply word by halfword
-


M4


SMUSD, SMUSDX
{Rd,} Rn, Rm
Signed dual Multiply Subtract
-

M3
M4
32

SSAT
Rd, #n, Rm {,shift #s}
Signed Saturate
Q


M4


SSAT16
Rd, #n, Rm
Signed Saturate 16
Q


M4


SSAX
{Rd,} Rn, Rm
Signed Subtract and Add with Exchange
GE


M4


SSUB16
{Rd,} Rn, Rm
Signed Subtract 16
-


M4


SSUB8
{Rd,} Rn, Rm
Signed Subtract 8
-
M0
M3
M4
32
Memory
STM
Rn!,reglist
Store Multiple registers, increment after
-

M3
M4

Memory
STMDB, STMEA
Rn!,reglist
Store Multiple registers, decrement before
-

M3
M4
16
Memory
STMFD, STMIA
Rn!,reglist
Store Multiple registers, increment after
-
M0
M3
M4
16
16/32
STR
Rt,[Rn,<Rm|#imm>]
Store Register as word
-
M0



Memory
STRB
Rt,[Rn,<Rm|#imm>]
Store Register as byte
-
=
M3
M4
16
16/32
STRB, STRBT
Rt, [Rn, #offset]
Store Register byte
-

M3
M4
32
Memory
STRD
Rt, Rt2, [Rn, #offset]
Store Register two words
-

M3
M4
32
Memory
STREX
Rd, Rt, [Rn, #offset]
Store Register Exclusive
-

M3
M4
32
Memory
STREXB
Rd, Rt, [Rn]
Store Register Exclusive Byte
-

M3
M4
32
Memory
STREXH
Rd, Rt, [Rn]
Store Register Exclusive Halfword
-
M0



Memory
STRH
Rt,[Rn,<Rm|#imm>]
Store Register as halfword
-
=
M3
M4
16
16/32
STRH, STRHT
Rt, [Rn, #offset]
Store Register as halfword
-

M3
M4

Memory
STRT
Rt, [Rn, #offset]
Store Register word
-
M0
M3
M4


SUB{S}
{Rd,}Rn,<Rm|#imm>
Subtract
N,Z,C,V

M3
M4
16
16/32
SUB, SUBW
{Rd,} Rn, #imm12
Subtract
N,Z,C,V
M0
M3
M4
16
SVC
#imm
Supervisor Call 系統任務調用
-


M4


SXTAB   
{Rd,} Rn, Rm,{,ROR #}
Extend 8 bits to 32 and add
-


M4


SXTAB16
{Rd,} Rn, Rm,{,ROR #}
Dual extend 8 bits to 16 and add
-


M4


SXTAH
{Rd,} Rn, Rm,{,ROR #}
Extend 16 bits to 32 and add
-


M4


SXTB16
{Rd,} Rm {,ROR #n}
Signed Extend Byte 16

M0




SXTB
Rd,Rm
Sign extend byte
-
=
M3
M4
16
16/32
SXTB
{Rd,} Rm {,ROR #n}
Sign extend byte
-
M0




SXTH
Rd,Rm
Sign extend halfword
-
=
M3
M4
16

SXTH
{Rd,} Rm {,ROR #n}
Sign extend halfword
-

M3
M4
32

TBB
[Rn, Rm]
Table Branch Byte
-

M3
M4
32

TBH
[Rn, Rm, LSL #1]
Table Branch Halfword
-

M3
M4
32

TEQ
Rn, Op2
Test Equivalence
N,Z,C
M0




TST
Rn,Rm
Logical AND based test
N,Z
=
M3
M4
16
16/32
TST
Rn, Op2
Test
N,Z,C


M4


UADD16
{Rd,} Rn, Rm
Unsigned Add 16
GE


M4


UADD8
{Rd,} Rn, Rm
Unsigned Add 8
GE


M4


USAX
{Rd,} Rn, Rm
Unsigned Subtract and Add with Exchange
GE


M4


UHADD16
{Rd,} Rn, Rm
Unsigned Halving Add 16
-


M4


UHADD8
{Rd,} Rn, Rm
Unsigned Halving Add 8
-


M4


UHASX
{Rd,} Rn, Rm
Unsigned Halving Add and Subtract with Exchange
-


M4


UHSAX
{Rd,} Rn, Rm
Unsigned Halving Subtract and Add with Exchange
-


M4


UHSUB16
{Rd,} Rn, Rm
Unsigned Halving Subtract 16
-


M4


UHSUB8
{Rd,} Rn, Rm
Unsigned Halving Subtract 8
-

M3
M4
32

UBFX
Rd, Rn, #lsb, #width
Unsigned Bit Field Extract
-

M3
M4
32

UDIV
{Rd,} Rn, Rm
Unsigned Divide
-


M4


UMAAL
RdLo, RdHi, Rn, Rm
Unsigned Multiply Accumulate Accumulate
Long (32 x32 + 32 +32), 64-bit result


M3
M4
32

UMLAL
RdLo, RdHi, Rn, Rm
Unsigned Multiply with Accumulate
(32 x 32 +64), 64-bit result


M3
M4
32

UMULL
RdLo, RdHi, Rn, Rm
Unsigned Multiply (32 x 32), 64-bit result
-


M4


UQADD16
{Rd,} Rn, Rm
Unsigned Saturating Add 16



M4


UQADD8
{Rd,} Rn, Rm
Unsigned Saturating Add 8
-


M4


UQASX
{Rd,} Rn, Rm
Unsigned Saturating Add and Subtract with Exchange
-


M4

UQSAX
{Rd,} Rn, Rm
Unsigned Saturating Subtract and Add with Exchange
-


M4


UQSUB16
{Rd,} Rn, Rm
Unsigned Saturating Subtract 16
-


M4


UQSUB8
{Rd,} Rn, Rm
Unsigned Saturating Subtract 8
-


M4


USAD8
{Rd,} Rn, Rm
Unsigned Sum of Absolute Differences
-


M4


USADA8
{Rd,} Rn, Rm, Ra
Unsigned Sum of Absolute Differences and Accumulate


M3
M4
32

USAT
Rd, #n, Rm {,shift #s}
Unsigned Saturate
Q


M4


USAT16
Rd, #n, Rm
Unsigned Saturate 16
Q


M4


UASX
{Rd,} Rn, Rm
Unsigned Add and Subtract with Exchange
GE


M4


USUB16
{Rd,} Rn, Rm
Unsigned Subtract 16
GE


M4


USUB8
{Rd,} Rn, Rm
Unsigned Subtract 8
GE


M4


UXTAB  
{Rd,} Rn, Rm,{,ROR #}
Rotate, extend 8 bits to 32 and Add
-


M4


UXTAB16
{Rd,} Rn, Rm,{,ROR #}
Rotate, dual extend 8 bits to 16 and Add
-


M4


UXTAH
{Rd,} Rn, Rm,{,ROR #}
Rotate, unsigned extend and Add Halfword
-
M0

M4


UXTB
Rd,Rm
Zero extend a byte
-
=
M3
M4
16
16/32
UXTB
{Rd,} Rm {,ROR #n}
Zero extend a byte
-


M4


UXTB16
{Rd,} Rm {,ROR #n}
Unsigned Extend Byte 16
-
M0




UXTH
Rd,Rm
Zero extend a halfword
-
=
M3
M4
16
16/32
UXTH
{Rd,} Rm {,ROR #n}
Zero extend a halfword
-


M4F


VABS.F32
Sd, Sm
Floating-point Absolute
-


M4F


VADD.F32
{Sd,} Sn, Sm
Floating-point Add
-


M4F


VCMP.F32
Sd, <Sm | #0.0>
Compare two floating-point registers, or one
Floating-point register and zero
FPSCR


M4F


VCMPE.F32
Sd, <Sm | #0.0>
Compare two floating-point registers, or one
Floating-point register and zero check



M4F


VCVT.S32.F32
Sd, Sm
Convert between floating-point and integer
-


M4F


VCVT.S16.F32   
Sd, Sd, #fbits
Convert between floating-point and fixed point
-


M4F


VCVTR.S32.F32
Sd, Sm
Convert between floating-point and integer with rounding
-


M4F


VCVT<B|H>.F32.F16
Sd, Sm
Converts half-precision value to single-precision
-


M4F


VCVTT<B|T>.F32.F16
Sd, Sm
Converts single-precision register to half-precision
-


M4F


VDIV.F32
{Sd,} Sn, Sm
Floating-point Divide
-


M4F


VFMA.F32
{Sd,} Sn, Sm
Floating-point Fused Multiply Accumulate
-


M4F


VFNMA.F32
{Sd,} Sn, Sm
Floating-point Fused Negate Multiply Accumulate
-


M4F


VFMS.F32
{Sd,} Sn, Sm
Floating-point Fused Multiply Subtract
-


M4F


VFNMS.F32
{Sd,} Sn, Sm
Floating-point Fused Negate Multiply Subtract
-


M4F


VLDM.F<32|64>   
Rn{!}, list
Load Multiple extension registers
-


M4F


VLDR.F<32|64>   
<Dd|Sd>, [Rn]
Load an extension register from memory
-


M4F


VLMA.F32
{Sd,} Sn, Sm
Floating-point Multiply Accumulate
-


M4F


VLMS.F32
{Sd,} Sn, Sm
Floating-point Multiply Subtract
-


M4F


VMOV.F32   
Sd, #imm
Floating-point Move immediate
-


M4


VMOV   
Sd, Sm
Floating-point Move register
-


M4


VMOV   
Sn, Rt
Copy ARM core register to single precision
-


M4


VMOV   
Sm, Sm1, Rt, Rt2
Copy 2 ARM core registers to 2 single precision
-


M4


VMOV   
Dd[x], Rt
Copy ARM core register to scalar
-


M4


VMOV   
Rt, Dn[x]
Copy scalar to ARM core register
-


M4


VMRS   
Rt, FPSCR
Move FPSCR to ARM core register or APSR
N,Z,C,V


M4


VMSR   
FPSCR, Rt
Move to FPSCR from ARM Core register
FPSCR


M4F


VMUL.F32
{Sd,} Sn, Sm
Floating-point Multiply
-


M4F


VNEG.F32
Sd, Sm
Floating-point Negate
-


M4F


VNMLA.F32
Sd, Sn, Sm
Floating-point Multiply and Add
-


M4F


VNMLS.F32
Sd, Sn, Sm
Floating-point Multiply and Subtract
-


M4


VNMUL
{Sd,} Sn, Sm
Floating-point Multiply
-


M4


VPOP
list
Pop extension registers
-


M4


VPUSH
list
Push extension registers
-


M4F


VSQRT.F32
Sd, Sm
Calculates floating-point Square Root
-


M4


VSTM   
Rn{!}, list
Floating-point register Store Multiple
-


M4F


VSTR.F<32|64>  
Sd, [Rn]
Stores an extension register to memory
-


M4F


VSUB.F<32|64>
{Sd,} Sn, Sm
Floating-point Subtract
-
M0
M3
M4
32
WFE
-
Wait For Event
-
M0
M3
M4
32
WFI
-
Wait For Interrupt
-

此内容由EEWORLD论坛网友yubinwu原创,如需转载或用于商业用途需征得作者同意并注明出处





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 楼主| 发表于 2018-8-8 16:30:22 | 显示全部楼层
好像宽度变了 arm m0 m3 m4.rar (22.89 KB, 下载次数: 5)


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发表于 2018-8-8 16:32:57 | 显示全部楼层
总结的很详细


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发表于 2018-8-9 07:33:20 | 显示全部楼层
谢谢分享!总结的很详细,很好,先收藏,慢慢研究^_^
专注智能产品的研究与开发,专注于电子电路的生产与制造……QQ:2912615383,电子爱好者群: 422240210


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