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仿真运行时出现找不到设计单元 work.module
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我的程序不能进入仿真,提示错误是:
# ** Error: Failed to find design unit work.module.
我以前也用过modelsim se-64 10.0C
altera11 和altera15 都测试了
# Top level modules:
# fifoIp_vlg_tst
#
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" module fifoIp_vlg_tst
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps module fifoIp_vlg_tst
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: Failed to find design unit work.module.
# Optimization failed
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./fifoIp_run_msim_rtl_verilog.do PAUSED at line 42
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