library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity jifei is
port(kmout:in std_logic;
enable:in std_logic;
reset:in std_logic;
count1,count2,count3,count4:out std_logic_vector(3 downto 0));
end jifei;
architecture one of jifei is
begin
process(kmout,reset)
variable q1,q2,q3,q4:std_logic_vector(3 downto 0);
constant a:std_logic_vector(3 downto 0):="0101";
begin
q2:=a;
if kmout'event and kmout='1' then
if reset='1' then
count1<="0000";count2<="0101";count3<="0000";count4<="0000";
elsif enable='0' then
count1<="0000";count2<="0101";count3<="0000";count4<="0000";
elsif enable='1' then
if q1<"0100" then
q1:=q1+6;
if q2<"1001" then
q2:=q2+1;
else q2:=q2-9;
if q3<"1001" then
q3:=q3+1;
else q3:="0000";
if q4<"1001" then
q4:=q4+1;
else q4:="0000";
end if;
end if;
end if;
else q1:=q1-4;
if q2<"1000" then
q2:=q2+2;
else q2:=q2-8;
if q3<"1001" then
q3:=q3+1;
else q3:="0000";
if q4<"1001" then
q4:=q4+1;
else q4:="0000";
end if;
end if;
end if;
end if;
count1<=q1;
count2<=q2;
count3<=q3;
count4<=q4;
end if;
end if;
end process;
end one;
程序如上
仿真如下