【FRDM-MCXN947】spi flash存储器读写测试
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本帖最后由 TL-LED 于 2024-12-18 16:36 编辑
spi flash存储器读写测试。
一、硬件连接
1.1、使用开发板的SPI相关的引脚
1.2、外部FLASH存储器电路图部分
二、配置SPI端口
2.1、配置FC1_SPI端口
2.2、SS端口配置
SS端口和LED_GREEN端口共用引脚
三、程序部分
3.1、spi_flash.c
/**
**************************************************************************
* [url=home.php?mod=space&uid=1307177]@File[/url] spi_flash.c
* [url=home.php?mod=space&uid=159083]@brief[/url] spi_flash source code
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#include "spiflash/spi_flash.h"
uint8_t spiflash_sector_buf[SPIF_SECTOR_SIZE];
void init_spi(void)
{
uint32_t srcClock_Hz;
lpspi_master_config_t masterConfig;
edma_config_t userConfig = {0};
/* attach FRO 12M to FLEXCOMM1 */
CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
init_spi1_pins();
/*Master config*/
LPSPI_MasterGetDefaultConfig(&masterConfig);
masterConfig.baudRate = TRANSFER_BAUDRATE;
masterConfig.whichPcs = EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT;
masterConfig.pcsToSckDelayInNanoSec = 1000000000U / (masterConfig.baudRate * 2U);
masterConfig.lastSckToPcsDelayInNanoSec = 1000000000U / (masterConfig.baudRate * 2U);
masterConfig.betweenTransferDelayInNanoSec = 1000000000U / (masterConfig.baudRate * 2U);
srcClock_Hz = LPSPI_MASTER_CLK_FREQ;
LPSPI_MasterInit(EXAMPLE_LPSPI_MASTER_BASEADDR, &masterConfig, srcClock_Hz);
}
uint8_t spi1_writedat(uint8_t dat)
{
uint8_t srcBuff[2];
uint8_t destBuff[2];
srcBuff[0]=dat;
lpspi_transfer_t masterXfer;
masterXfer.txData = srcBuff;
masterXfer.rxData = destBuff;
masterXfer.dataSize = 1;
masterXfer.configFlags =
EXAMPLE_LPSPI_MASTER_PCS_FOR_TRANSFER | kLPSPI_MasterPcsContinuous | kLPSPI_MasterByteSwap;
LPSPI_MasterTransferBlocking(EXAMPLE_LPSPI_MASTER_BASEADDR, &masterXfer);
return destBuff[0];
}
/**
* @brief spi configuration.
* @param none
* @retval none
*/
void spiflash_init(void)
{
init_spi();
}
/**
* @brief write data to flash
* @param pbuffer: the pointer for data buffer
* @param write_addr: the address where the data is written
* @param length: buffer length
* @retval none
*/
void spiflash_write(uint8_t *pbuffer, uint32_t write_addr, uint32_t length)
{
uint32_t sector_pos;
uint16_t sector_offset;
uint16_t sector_remain;
uint16_t index;
uint8_t *spiflash_buf;
spiflash_buf = spiflash_sector_buf;
/* sector address */
sector_pos = write_addr / SPIF_SECTOR_SIZE;
/* address offset in a sector */
sector_offset = write_addr % SPIF_SECTOR_SIZE;
/* the remain in a sector */
sector_remain = SPIF_SECTOR_SIZE - sector_offset;
if(length <= sector_remain)
{
/* smaller than a sector size */
sector_remain = length;
}
while(1)
{
/* read a sector */
spiflash_read(spiflash_buf, sector_pos * SPIF_SECTOR_SIZE, SPIF_SECTOR_SIZE);
/* validate the read erea */
for(index = 0; index < sector_remain; index++)
{
if(spiflash_buf[sector_offset + index] != 0xFF)
{
/* there are some data not equal 0xff, so this secotr needs erased */
break;
}
}
if(index < sector_remain)
{
/* erase the sector */
spiflash_sector_erase(sector_pos);
/* copy the write data */
for(index = 0; index < sector_remain; index++)
{
spiflash_buf[index + sector_offset] = pbuffer[index];
}
spiflash_write_nocheck(spiflash_buf, sector_pos * SPIF_SECTOR_SIZE, SPIF_SECTOR_SIZE); /* program the sector */
}
else
{
/* write directly in the erased area */
spiflash_write_nocheck(pbuffer, write_addr, sector_remain);
}
if(length == sector_remain)
{
/* write end */
break;
}
else
{
/* go on writing */
sector_pos++;
sector_offset = 0;
pbuffer += sector_remain;
write_addr += sector_remain;
length -= sector_remain;
if(length > SPIF_SECTOR_SIZE)
{
/* could not write the remain data in the next sector */
sector_remain = SPIF_SECTOR_SIZE;
}
else
{
/* could write the remain data in the next sector */
sector_remain = length;
}
}
}
}
/**
* @brief read data from flash
* @param pbuffer: the pointer for data buffer
* @param read_addr: the address where the data is read
* @param length: buffer length
* @retval none
*/
void spiflash_read(uint8_t *pbuffer, uint32_t read_addr, uint32_t length)
{
FLASH_CS_LOW();
spi_byte_write(SPIF_READDATA); /* send instruction */
spi_byte_write((uint8_t)((read_addr) >> 16)); /* send 24-bit address */
spi_byte_write((uint8_t)((read_addr) >> 8));
spi_byte_write((uint8_t)read_addr);
spi_bytes_read(pbuffer, length);
FLASH_CS_HIGH();
}
/**
* @brief erase a sector data
* @param erase_addr: sector address to erase
* @retval none
*/
void spiflash_sector_erase(uint32_t erase_addr)
{
erase_addr *= SPIF_SECTOR_SIZE; /* translate sector address to byte address */
spiflash_write_enable();
spiflash_wait_busy();
FLASH_CS_LOW();
spi_byte_write(SPIF_SECTORERASE);
spi_byte_write((uint8_t)((erase_addr) >> 16));
spi_byte_write((uint8_t)((erase_addr) >> 8));
spi_byte_write((uint8_t)erase_addr);
FLASH_CS_HIGH();
spiflash_wait_busy();
}
/**
* @brief write data without check
* @param pbuffer: the pointer for data buffer
* @param write_addr: the address where the data is written
* @param length: buffer length
* @retval none
*/
void spiflash_write_nocheck(uint8_t *pbuffer, uint32_t write_addr, uint32_t length)
{
uint16_t page_remain;
/* remain bytes in a page */
page_remain = SPIF_PAGE_SIZE - write_addr % SPIF_PAGE_SIZE;
if(length <= page_remain)
{
/* smaller than a page size */
page_remain = length;
}
while(1)
{
spiflash_page_write(pbuffer, write_addr, page_remain);
if(length == page_remain)
{
/* all data are programmed */
break;
}
else
{
/* length > page_remain */
pbuffer += page_remain;
write_addr += page_remain;
/* the remain bytes to be prorammed */
length -= page_remain;
if(length > SPIF_PAGE_SIZE)
{
/* can be progrmmed a page at a time */
page_remain = SPIF_PAGE_SIZE;
}
else
{
/* smaller than a page size */
page_remain = length;
}
}
}
}
/**
* @brief write a page data
* @param pbuffer: the pointer for data buffer
* @param write_addr: the address where the data is written
* @param length: buffer length
* @retval none
*/
void spiflash_page_write(uint8_t *pbuffer, uint32_t write_addr, uint32_t length)
{
if((0 < length) && (length <= SPIF_PAGE_SIZE))
{
/* set write enable */
spiflash_write_enable();
FLASH_CS_LOW();
/* send instruction */
spi_byte_write(SPIF_PAGEPROGRAM);
/* send 24-bit address */
spi_byte_write((uint8_t)((write_addr) >> 16));
spi_byte_write((uint8_t)((write_addr) >> 8));
spi_byte_write((uint8_t)write_addr);
spi_bytes_write(pbuffer,length);
FLASH_CS_HIGH();
/* wait for program end */
spiflash_wait_busy();
}
}
/**
* @brief write data continuously
* @param pbuffer: the pointer for data buffer
* @param length: buffer length
* @retval none
*/
void spi_bytes_write(uint8_t *pbuffer, uint32_t length)
{
volatile uint8_t dummy_data;
#if defined(SPI_TRANS_DMA)
dma_init_type dma_init_struct;
dma_reset(DMA1_CHANNEL2);
dma_reset(DMA1_CHANNEL3);
dma_flexible_config(DMA1, FLEX_CHANNEL2, DMA_FLEXIBLE_SPI2_RX);
dma_flexible_config(DMA1, FLEX_CHANNEL3, DMA_FLEXIBLE_SPI2_TX);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = length;
dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_base_addr = (uint32_t)&dummy_data;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = FALSE;
dma_init_struct.peripheral_base_addr = (uint32_t)(&SPI2->dt);
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_VERY_HIGH;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL2, &dma_init_struct);
dma_init_struct.buffer_size = length;
dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_base_addr = (uint32_t)pbuffer;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)(&SPI2->dt);
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_VERY_HIGH;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL3, &dma_init_struct);
spi_i2s_dma_transmitter_enable(SPI2, TRUE);
spi_i2s_dma_receiver_enable(SPI2, TRUE);
dma_channel_enable(DMA1_CHANNEL2, TRUE);
dma_channel_enable(DMA1_CHANNEL3, TRUE);
while(dma_flag_get(DMA1_FDT2_FLAG) == RESET);
dma_flag_clear(DMA1_FDT2_FLAG);
dma_channel_enable(DMA1_CHANNEL2, FALSE);
dma_channel_enable(DMA1_CHANNEL3, FALSE);
spi_i2s_dma_transmitter_enable(SPI2, FALSE);
spi_i2s_dma_receiver_enable(SPI2, FALSE);
#else
while(length--)
{
dummy_data = spi1_writedat(*pbuffer);
pbuffer++;
}
#endif
}
/**
* @brief read data continuously
* @param pbuffer: buffer to save data
* @param length: buffer length
* @retval none
*/
void spi_bytes_read(uint8_t *pbuffer, uint32_t length)
{
uint8_t write_value = FLASH_SPI_DUMMY_BYTE;
#if defined(SPI_TRANS_DMA)
dma_init_type dma_init_struct;
dma_reset(DMA1_CHANNEL2);
dma_reset(DMA1_CHANNEL3);
dma_flexible_config(DMA1, FLEX_CHANNEL2, DMA_FLEXIBLE_SPI2_RX);
dma_flexible_config(DMA1, FLEX_CHANNEL3, DMA_FLEXIBLE_SPI2_TX);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = length;
dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_base_addr = (uint32_t)&write_value;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = FALSE;
dma_init_struct.peripheral_base_addr = (uint32_t)(&SPI2->dt);
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_VERY_HIGH;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL3, &dma_init_struct);
dma_init_struct.buffer_size = length;
dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_base_addr = (uint32_t)pbuffer;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)(&SPI2->dt);
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_VERY_HIGH;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL2, &dma_init_struct);
spi_i2s_dma_transmitter_enable(SPI2, TRUE);
spi_i2s_dma_receiver_enable(SPI2, TRUE);
dma_channel_enable(DMA1_CHANNEL2, TRUE);
dma_channel_enable(DMA1_CHANNEL3, TRUE);
while(dma_flag_get(DMA1_FDT2_FLAG) == RESET);
dma_flag_clear(DMA1_FDT2_FLAG);
dma_channel_enable(DMA1_CHANNEL2, FALSE);
dma_channel_enable(DMA1_CHANNEL3, FALSE);
spi_i2s_dma_transmitter_enable(SPI2, FALSE);
spi_i2s_dma_receiver_enable(SPI2, FALSE);
#else
while(length--)
{
*pbuffer = spi1_writedat(write_value);
pbuffer++;
}
#endif
}
/**
* @brief wait program done
* @param none
* @retval none
*/
void spiflash_wait_busy(void)
{
while((spiflash_read_sr1() & 0x01) == 0x01);
}
/**
* @brief read sr1 register
* @param none
* @retval none
*/
uint8_t spiflash_read_sr1(void)
{
uint8_t breadbyte = 0;
FLASH_CS_LOW();
spi_byte_write(SPIF_READSTATUSREG1);
breadbyte = (uint8_t)spi_byte_read();
FLASH_CS_HIGH();
return (breadbyte);
}
/**
* @brief enable write operation
* @param none
* @retval none
*/
void spiflash_write_enable(void)
{
FLASH_CS_LOW();
spi_byte_write(SPIF_WRITEENABLE);
FLASH_CS_HIGH();
}
/**
* @brief read device id
* @param none
* @retval device id
*/
uint16_t spiflash_read_id(void)
{
uint16_t wreceivedata = 0;
FLASH_CS_LOW();
spi_byte_write(SPIF_MANUFACTDEVICEID);
spi_byte_write(0x00);
spi_byte_write(0x00);
spi_byte_write(0x00);
wreceivedata |= spi_byte_read() << 8;
wreceivedata |= spi_byte_read();
FLASH_CS_HIGH();
return wreceivedata;
}
/**
* @brief write a byte to flash
* @param data: data to write
* @retval flash return data
*/
uint8_t spi_byte_write(uint8_t data)
{
uint8_t brxbuff;
brxbuff = spi1_writedat(data);
return brxbuff;
}
/**
* @brief read a byte to flash
* @param none
* @retval flash return data
*/
uint8_t spi_byte_read(void)
{
return (spi_byte_write(FLASH_SPI_DUMMY_BYTE));
}
/**
* @}
*/
/**
* @}
*/
3.2、spi_flash.h
/**
**************************************************************************
* @file spi_flash.h
* @brief header file of spi_flash
**************************************************************************
* Copyright notice & Disclaimer
*
* The software Board Support Package (BSP) that is made available to
* download from Artery official website is the copyrighted work of Artery.
* Artery authorizes customers to use, copy, and distribute the BSP
* software and its related documentation for the purpose of design and
* development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
*
**************************************************************************
*/
#ifndef __SPI_FLASH_H
#define __SPI_FLASH_H
#include "main.h"
/** @addtogroup AT32L021_periph_examples
* @{
*/
/** @addtogroup 021_SPI_w25q_flash
* @{
*/
/* use dma transfer spi data */
//#define SPI_TRANS_DMA
/** @defgroup SPI_flash_cs_pin_definition
* @{
*/
#define FLASH_CS_HIGH() GPIO_PortSet(LED_GREEN_GPIO, 1u << LED_GREEN_GPIO_PIN)
#define FLASH_CS_LOW() GPIO_PortClear(LED_GREEN_GPIO, 1u << LED_GREEN_GPIO_PIN)
/**
* @}
*/
/** @defgroup SPI_flash_id_definition
* @{
*/
/*
* flash define
*/
#define W25Q80 0xEF13
#define W25Q16 0xEF14
#define W25Q32 0xEF15
#define W25Q64 0xEF16
/* 16mb, the range of address:0~0xFFFFFF */
#define W25Q128 0xEF17
/**
* @}
*/
/** @defgroup SPI_flash_operation_definition
* @{
*/
#define SPIF_CHIP_SIZE 0x1000000
#define SPIF_SECTOR_SIZE 4096
#define SPIF_PAGE_SIZE 256
#define SPIF_WRITEENABLE 0x06
#define SPIF_WRITEDISABLE 0x04
/* s7-s0 */
#define SPIF_READSTATUSREG1 0x05
#define SPIF_WRITESTATUSREG1 0x01
/* s15-s8 */
#define SPIF_READSTATUSREG2 0x35
#define SPIF_WRITESTATUSREG2 0x31
/* s23-s16 */
#define SPIF_READSTATUSREG3 0x15
#define SPIF_WRITESTATUSREG3 0x11
#define SPIF_READDATA 0x03
#define SPIF_FASTREADDATA 0x0B
#define SPIF_FASTREADDUAL 0x3B
#define SPIF_PAGEPROGRAM 0x02
/* block size:64kb */
#define SPIF_BLOCKERASE 0xD8
#define SPIF_SECTORERASE 0x20
#define SPIF_CHIPERASE 0xC7
#define SPIF_POWERDOWN 0xB9
#define SPIF_RELEASEPOWERDOWN 0xAB
#define SPIF_DEVICEID 0xAB
#define SPIF_MANUFACTDEVICEID 0x90
#define SPIF_JEDECDEVICEID 0x9F
#define FLASH_SPI_DUMMY_BYTE 0xA5
/**
* @}
*/
/** @defgroup SPI_flash_exported_functions
* @{
*/
void spiflash_init(void);
void spiflash_write(uint8_t *pbuffer, uint32_t write_addr, uint32_t length);
void spiflash_read(uint8_t *pbuffer, uint32_t read_addr, uint32_t length);
void spiflash_sector_erase(uint32_t erase_addr);
void spiflash_write_nocheck(uint8_t *pbuffer, uint32_t write_addr, uint32_t length);
void spiflash_page_write(uint8_t *pbuffer, uint32_t write_addr, uint32_t length);
void spi_bytes_write(uint8_t *pbuffer, uint32_t length);
void spi_bytes_read(uint8_t *pbuffer, uint32_t length);
void spiflash_wait_busy(void);
uint8_t spiflash_read_sr1(void);
void spiflash_write_enable(void);
uint16_t spiflash_read_id(void);
uint8_t spi_byte_write(uint8_t data);
uint8_t spi_byte_read(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif
3.3、fun_task.c
#include "main.h"
#define FLASH_TEST_ADDR 0x1000
#define SPI_BUF_SIZE 256
uint8_t tx_buffer[SPI_BUF_SIZE];
uint8_t rx_buffer[SPI_BUF_SIZE];
#define START_TASK_PRO 1
#define START_STK_SIZE 128
TaskHandle_t StartTask_Handler;
#define TASK1_PRIO 4
#define TASK1_STK_SIZE 128
static TaskHandle_t Task1Task_Handler = NULL;
#define TASK2_PRIO 3
#define TASK2_STK_SIZE 128
static TaskHandle_t Task2Task_Handler = NULL;
void start_task(void *pvParameters);
void gui_task(void *pvParameters);
void task1(void *pvParameters);
void task2(void *pvParameters);
void tx_data_fill(void)
{
uint32_t data_index = 0;
for(data_index = 0; data_index < SPI_BUF_SIZE; data_index++)
{
tx_buffer[data_index] = 255-data_index;
}
}
void task_create(void)
{
//start_task
xTaskCreate((TaskFunction_t )start_task,
(const char* )"start_task",
(uint16_t )START_STK_SIZE,
(void* )NULL,
(UBaseType_t )START_TASK_PRO,
(TaskHandle_t* )&StartTask_Handler);
vTaskStartScheduler();
}
void start_task(void *pvParameters)
{
taskENTER_CRITICAL();
//task1
xTaskCreate((TaskFunction_t )task1,
(const char* )"task1",
(uint16_t )TASK1_STK_SIZE,
(void* )NULL,
(UBaseType_t )TASK1_PRIO,
(TaskHandle_t* )&Task1Task_Handler);
//task2
xTaskCreate((TaskFunction_t )task2,
(const char* )"task2",
(uint16_t )TASK2_STK_SIZE,
(void* )NULL,
(UBaseType_t )TASK2_PRIO,
(TaskHandle_t* )&Task2Task_Handler);
taskEXIT_CRITICAL();
vTaskDelete(StartTask_Handler);
}
//task1
void task1(void *pvParameters)
{
__IO uint32_t index = 0;
__IO uint32_t flash_id_index = 0;
tx_data_fill();
spiflash_init();
flash_id_index = spiflash_read_id();
if(flash_id_index !=0x5114)
{
PRINTF("flash id check error!\r\n");
}
else
{
PRINTF("flash id check success! id: %x\r\n", flash_id_index);
}
spiflash_sector_erase(FLASH_TEST_ADDR / SPIF_SECTOR_SIZE);
spiflash_write(tx_buffer, FLASH_TEST_ADDR, SPI_BUF_SIZE);
spiflash_read(rx_buffer, FLASH_TEST_ADDR, SPI_BUF_SIZE);
PRINTF("Read Data: ");
for(index = 0; index < SPI_BUF_SIZE; index++)
{
PRINTF("%x ", rx_buffer[index]);
}
while (1)
{
//PRINTF("task1 run ...\r\n");
vTaskDelay(200);
}
}
//task2
void task2(void *pvParameters)
{
while (1)
{
//PRINTF("task2 run ...\r\n");
vTaskDelay(100);
}
}
四、运行结果
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