【Perf-V评测】之 8段数码管

eew_3sqZMg · 最新更新于2021-01-21 19:54

【Perf-V评测】之 8段数码管 [复制链接]

本帖最后由 eew_3sqZMg 于 2021-1-28 17:32 编辑

澎峰的Demo里还真没有七段数码管的实验，可能这种太基础的大佬们都没看在眼里。对我等小白来说做个数码管实验还是能找找存在感滴。标题叫8段数码管是因为目前七段数码管都带一个小数点DP，因此就成了8段，但大家还是习惯叫七段数码管。搜索了一番我的盒子，总算找到俩个数码管。比较MINI，不知道是共阴还是共阳。

用万用表测量了一下，是共阳极二极管。

其中左上角1号脚和右下角6号脚是公共阳极，2-5号，7-10分别对应于f\g\e\d\dp\c\b\a段发光二极管。数码管有了，接着确定该怎么跟板子连接。Perf-V的板子最容易连接的就是开发板的arduino接口，接口每个引脚都有200欧的限流电阻，可以用杜邦线将数码管跟接口连接。

这里，用开发板的D5-D12分别连接数码管的a\b\c\dp\3.3v\d\e\g\f引脚。

时钟选择开发板外部输入的50MHz时钟作为输入。

电源输入选择板子上的3.3v电源输入。

接下来开始写verilog代码：

module decoder_7_seg(
input CLK,
input [3:0] D,
output reg [7:0] SEG
);
always @(posedge CLK)
begin
case(D)
4'd0: SEG <= 8'b00000011;
4'd1: SEG <= 8'b10011111;
4'd2: SEG <= 8'b00100101;
4'd3: SEG <= 8'b00001101;
4'd4: SEG <= 8'b10011001;
4'd5: SEG <= 8'b01001001;
4'd6: SEG <= 8'b01000001;
4'd7: SEG <= 8'b00011111;
4'd8: SEG <= 8'b00000001;
4'd9: SEG <= 8'b00001001;
default: SEG <= 8'b11111111;
endcase
end
endmodule

编译、综合实现过程都类似，分配引脚时尤其要注意高低位跟数码管的分段对应好，xdc引脚约束如下：

set_property IOSTANDARD LVCMOS33 [get_ports {D[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[0]}]
set_property PACKAGE_PIN K13 [get_ports {D[0]}]
set_property PACKAGE_PIN L14 [get_ports {D[1]}]
set_property PACKAGE_PIN T15 [get_ports {D[3]}]
set_property PACKAGE_PIN N14 [get_ports CLK]
set_property IOSTANDARD LVCMOS33 [get_ports CLK]
set_property PACKAGE_PIN N13 [get_ports {SEG[7]}]
set_property PACKAGE_PIN R11 [get_ports {SEG[6]}]
set_property PACKAGE_PIN R10 [get_ports {SEG[5]}]
set_property PACKAGE_PIN T5 [get_ports {SEG[4]}]
set_property PACKAGE_PIN R6 [get_ports {SEG[3]}]
set_property PACKAGE_PIN R13 [get_ports {SEG[2]}]
set_property PACKAGE_PIN R7 [get_ports {SEG[1]}]
set_property PACKAGE_PIN T13 [get_ports {SEG[0]}]
set_property PACKAGE_PIN M14 [get_ports {D[2]}]