社区导航

 

搜索
查看: 2253|回复: 0

[讨论] Crossing clock domains - Signal

[复制链接]

8910

TA的帖子

0

TA的资源

五彩晶圆(高级)

Rank: 9Rank: 9Rank: 9

发表于 2010-6-22 19:10 | 显示全部楼层 |阅读模式
A signal to another clock domain

Let's say a signal from clkA domain is needed in clkB domain. It needs to be "synchronized" to clkB domain, so we want to build a "synchronizer" design, which takes a signal from clkA domain, and creates a new signal into clkB domain.

In this first design, we assume that the signal-in changes "slowly" compared to both clkA and clkB clock speeds.
Typically all you need to do is to use two flip-flops to move the signal from clkA to clkB (to learn why, get back to the links).

module Signal_CrossDomain(
    clkA, SignalIn, 
    clkB, SignalOut);

// clkA domain signals
input clkA;
input SignalIn;

// clkB domain signals
input clkB;
output SignalOut;

// Now let's transfer SignalIn into the clkB clock domain
// We use a two-stages shift-register to synchronize the signal
reg [1:0] SyncA_clkB;
always @(posedge clkB) SyncA_clkB[0] <= SignalIn;      // notice that we use clkB
always @(posedge clkB) SyncA_clkB[1] <= SyncA_clkB[0]; // notice that we use clkB

assign SignalOut = SyncA_clkB[1];  // new signal synchronized to (=ready to be used in) clkB domain
endmodule

The two flip-flops have the side-effect of delaying the signal.
For example, here are waveforms where you can see the slow moving signal being synchronized (and delayed) to clkB domain by the two flip-flops:

 

原汁原味的异步处理方法,参考上面的E文!

此帖出自FPGA/CPLD论坛
一个为理想不懈前进的人,一个永不言败人!
http://shop57496282.taobao.com/
欢迎光临网上店铺!


您需要登录后才可以回帖 登录 | 注册

关闭

站长推荐上一条 /5 下一条

  • 论坛活动 E手掌握

    扫码关注
    EEWORLD 官方微信

  • EE福利  唾手可得

    扫码关注
    EE福利 唾手可得

Archiver|手机版|小黑屋|电子工程世界 ( 京ICP证 060456 )

GMT+8, 2020-2-22 06:16 , Processed in 0.079950 second(s), 18 queries , Gzip On, MemCache On.

快速回复 返回顶部 返回列表