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FPGA实验(四)基于HDL语言的PWM呼吸灯
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Verilog HDL语言学习一、PWM波呼吸灯(高四位和低四位灯光亮度对比,占空比固定)
- module PWM_LED(
- input ext_clk_50M,
-
- output reg[3:0]LED
- );
- reg [31:0]cnt;
- reg [7:0]num;
- reg div_50_clk;
- always [url=home.php?mod=space&uid=775551]@[/url] (posedge ext_clk_50M)
- if(cnt == 32'd50)
- begin
- cnt <= 0;
- div_50_clk <= ~div_50_clk;
- end
- else cnt <= cnt + 32'd1;
- always @ (posedge ext_clk_50M)
- if(num == 8'd100)num <= 8'd0;
- else num <= num + 8'd1;
- always @ (posedge div_50_clk)
- if(num > 90)LED <= 4'b0000;
- else LED <= 4'b1111;
- endmodule
-
复制代码
视频演示效果如下:
PWM呼吸灯(占空比固定).mp4
(1.05 MB, 下载次数: 6)
一、PWM波呼吸灯(占空比按键可调,状态机按键消抖处理)
- module PWM_LED(
- input ext_clk_50M,
- input key_in,
- output reg[3:0]LED
- );
- parameter s0 = 2'b00,s1 = 2'b01,s2 = 2'b10,s3 = 2'b11;
- reg key_out;
- reg[1:0]state;
- reg [31:0]cnt;
- reg [7:0]num;
- reg [7:0]flag;
- reg div_50_clk;
- always @ (posedge ext_clk_50M)
- case(state)
- s0:
- begin
- key_out <= 1'b1;
- if(key_in == 1'b0) state <= s1;
- else state <= s0;
- end
- s1:
- begin
- if(key_in == 1'b0) state <= s2;
- else state <= s0;
- end
- s2:
- begin
- if(key_in == 1'b0) state <= s3;
- else state <= s0;
- end
- s3:
- begin
- if(key_in == 1'b0)
- begin
- key_out <= 1'b0;
- state <= s3;
- end
- else
- begin
- key_out <= 1'b1;
- state <= s0;
- end
- end
- default:state <= s0;
- endcase
-
- always @ (negedge key_out)
- if(flag == 8'd100) flag <= 8'd0;
- else flag <= flag + 8'd10;
- always @ (posedge ext_clk_50M)
- if(cnt == 32'd50)
- begin
- cnt <= 0;
- div_50_clk <= ~div_50_clk;
- end
- else cnt <= cnt + 32'd1;
- always @ (posedge ext_clk_50M)
- if(num == 8'd100)num <= 8'd0;
- else num <= num + 8'd1;
- always @ (posedge div_50_clk)
- if(num > flag)LED <= 4'b0000;
- else LED <= 4'b1111;
- endmodule
-
复制代码
视频演示效果如下:
PWM呼吸灯(状态机按键消抖PWM可调).mp4
(1.84 MB, 下载次数: 4)
工程文件分享如下:
3.1、PWM波呼吸灯(高四位和低四位对比).rar
(352.29 KB, 下载次数: 0)
3.2、PWM波(锁定特定引脚74用示波器观看).rar
(349.33 KB, 下载次数: 0)
3.3、PWM波呼吸灯(按键可调).rar
(402.98 KB, 下载次数: 0)
希望能帮到大家,欢迎讨论!
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