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[求助] altera DDR3 ip调用综合pll配置失败

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一粒金砂(中级)

Rank: 2

发表于 2018-10-9 22:27:31 | 显示全部楼层 |阅读模式
altera cyclonev调用ddr3 ip。折腾了好长时间,结果还是不对,软件告诉我pll不对,实际上这个pll是ddrip内部的。一直到不到原因,求指导,搞不出来压力好大。pll有6个,就用了1个而已。找不到是什么原因导致的。综合能过,就是不能place&route。时钟输入引脚位N9,是clk_p时钟引脚。按理说是没有什么问题的。还发现将此引脚分配去掉后就不会报错。具体错误如下:
Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 fractional PLL(s))
        Error (175020): Illegal constraint of fractional PLL that is part of DDR3 SDRAM Controller with UniPHY ddr3 to the region (0, 0) to (0, 8): no valid locations in region
                Info (14596): Information about the failing component:
                        Info (175028): The fractional PLL name: ddr3:u3_ddr3|ddr3_0002:ddr3_inst|ddr3_pll0:pll0|pll1~FRACTIONAL_PLL
                Info (175013): The fractional PLL is constrained to the region (0, 0) to (0, 8) due to related logic
                        Info (175015): The I/O pad mem_dm[0] is constrained to the location PIN_AB18 due to: User Location Constraints (PIN_AB18)
                        Info (14709): The constrained I/O pad is driven by a DLL, which is driven by this fractional PLL
                Error (11238): Node is not compatible with other nodes placed at the same location either because there are too few available fractional PLL locations, or the nodes have different inputs, parameters, or both.
                        Error (11239): Could not merge with previously placed fractional PLLs at location FRACTIONALPLL_X0_Y1_N0
                                Info (11237): Already placed at this location: fractional PLL PLL:U_PLL|PLL_0002:pll_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
                                        Info (175013): The fractional PLL is constrained to the region (0, 0) to (0, 8) due to related logic
                                                Info (175015): The I/O pad mem_dm[0] is constrained to the location PIN_AB18 due to: User Location Constraints (PIN_AB18)
                                                Info (14709): The constrained I/O pad is driven by a DLL, which is driven by a fractional PLL, which is driven by a pin, which drives this fractional PLL
官方例程用的型号和我工程型号不一样,官方的(Cyclone V:5CGX****)可以编译通过,改成我的型号(Cyclone V: 5CEFA5F23I7)就不行了。

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一粒金砂(初级)

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发表于 2018-10-12 13:17:13 | 显示全部楼层
你自己重新生成已给PLL试试!


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